MSR_IA32_XSS
: "c" (MSR_IA32_XSS));
raw_rdmsr(MSR_IA32_XSS, &m);
wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() |
wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor());
wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask);
wrmsrq(MSR_IA32_XSS, xfeatures_mask_supervisor() |
__kvm_emulate_msr_write(vcpu, MSR_IA32_XSS, kvm_ghcb_get_xss(svm));
svm_set_intercept_for_msr(vcpu, MSR_IA32_XSS, MSR_TYPE_RW,
msr_info->index != MSR_IA32_XSS &&
wrmsrl(MSR_IA32_XSS, kvm_host.xss);
rdmsrq(MSR_IA32_XSS, kvm_host.xss);
wrmsrq(MSR_IA32_XSS, load_guest ? vcpu->arch.ia32_xss : kvm_host.xss);
kvm_msr_write(vcpu, MSR_IA32_XSS, 0);
MSR_IA32_XFD, MSR_IA32_XFD_ERR, MSR_IA32_XSS,
case MSR_IA32_XSS:
case MSR_IA32_XSS:
case MSR_IA32_XSS:
data = test_rdmsr(MSR_IA32_XSS);
test_wrmsr(MSR_IA32_XSS, 0);
test_wrmsr(MSR_IA32_XSS, 1);
.base = MSR_IA32_XSS,
data = test_em_rdmsr(MSR_IA32_XSS);
test_em_wrmsr(MSR_IA32_XSS, 0);
test_em_wrmsr(MSR_IA32_XSS, 1);
case MSR_IA32_XSS:
case MSR_IA32_XSS:
run_guest_then_process_rdmsr(vcpu, MSR_IA32_XSS);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_XSS);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_XSS);
run_guest_then_process_rdmsr(vcpu, MSR_IA32_XSS);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_XSS);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_XSS);
xss_val = vcpu_get_msr(vcpu, MSR_IA32_XSS);
vcpu_set_msr(vcpu, MSR_IA32_XSS, xss_val);
xss_in_msr_list = kvm_msr_is_in_save_restore_list(MSR_IA32_XSS);
r = _vcpu_set_msr(vcpu, MSR_IA32_XSS, 1ull << i);