MSR_IA32_TSC
case MSR_IA32_TSC:
ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
if (msr_index == MSR_IA32_TSC && vmx->nested.tsc_autostore_slot >= 0) {
if (nested_msr_store_list_has_msr(&vmx->vcpu, MSR_IA32_TSC) &&
vmx->msr_autostore.val[vmx->msr_autostore.nr].index = MSR_IA32_TSC;
vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R);
MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
case MSR_IA32_TSC:
case MSR_IA32_TSC: {
return msr != MSR_IA32_TSC;
wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE);
wrmsr(MSR_IA32_TSC, rdtsc() - TSC_ADJUST_VALUE);
tsc_start = rdmsr(MSR_IA32_TSC);
tsc_end = rdmsr(MSR_IA32_TSC);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
vcpu_set_msr(vcpu, MSR_IA32_TSC, HOST_ADJUST + val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
TEST_ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
wrmsr(MSR_IA32_TSC, val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);
wrmsr(MSR_IA32_TSC, val);
GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);
vcpu_set_msr(vcpu, MSR_IA32_TSC, TEST_TSC_OFFSET);