arch/mips/kernel/irq-msc01.c

122

MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);

arch/mips/kernel/irq-msc01.c

136

MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);

arch/mips/kernel/irq-msc01.c

138

MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);

arch/mips/kernel/irq-msc01.c

146

MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);

arch/mips/kernel/irq-msc01.c

148

MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);

arch/mips/kernel/irq-msc01.c

154

MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */

arch/mips/kernel/irq-msc01.c

32

MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));

arch/mips/kernel/irq-msc01.c

34

MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));

arch/mips/kernel/irq-msc01.c

43

MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));

arch/mips/kernel/irq-msc01.c

45

MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));

arch/mips/kernel/irq-msc01.c

55

MSCIC_WRITE(MSC01_IC_EOI, 0);

arch/mips/kernel/irq-msc01.c

67

MSCIC_WRITE(MSC01_IC_EOI, 0);

arch/mips/kernel/irq-msc01.c

71

MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);

arch/mips/kernel/irq-msc01.c

72

MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);

arch/mips/kernel/irq-msc01.c

94

MSCIC_WRITE(MSC01_IC_RAMW,