MSR_IA32_FLUSH_CMD
MSR_IA32_FLUSH_CMD,
svm_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,
nested_vmx_merge_msr_bitmaps_write(MSR_IA32_FLUSH_CMD);
native_wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
vmx_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W,
case MSR_IA32_FLUSH_CMD:
wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
wrmsrq(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
test_rdmsr(MSR_IA32_FLUSH_CMD);
test_wrmsr(MSR_IA32_FLUSH_CMD, 0);
test_wrmsr(MSR_IA32_FLUSH_CMD, 1);
test_em_rdmsr(MSR_IA32_FLUSH_CMD);
test_em_wrmsr(MSR_IA32_FLUSH_CMD, 0);
test_em_wrmsr(MSR_IA32_FLUSH_CMD, 1);
.base = MSR_IA32_FLUSH_CMD,
case MSR_IA32_FLUSH_CMD:
case MSR_IA32_FLUSH_CMD:
run_guest_then_process_rdmsr(vcpu, MSR_IA32_FLUSH_CMD);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_FLUSH_CMD);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_FLUSH_CMD);
run_guest_then_process_rdmsr(vcpu, MSR_IA32_FLUSH_CMD);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_FLUSH_CMD);
run_guest_then_process_wrmsr(vcpu, MSR_IA32_FLUSH_CMD);