arch/x86/hyperv/hv_crash.c

167

hv_wrmsr(MSR_IA32_CR_PAT, hv_crash_ctxt.pat);

arch/x86/hyperv/hv_crash.c

222

ctxt->pat = __rdmsr(MSR_IA32_CR_PAT);

arch/x86/hyperv/hv_vtl.c

169

input->vp_context.msr_cr_pat = native_rdmsrq(MSR_IA32_CR_PAT);

arch/x86/kvm/svm/sev.c

4559

svm_disable_intercept_for_msr(vcpu, MSR_IA32_CR_PAT, MSR_TYPE_RW);

arch/x86/kvm/svm/svm.c

2938

case MSR_IA32_CR_PAT:

arch/x86/kvm/vmx/tdx.c

2110

case MSR_IA32_CR_PAT:

arch/x86/kvm/vmx/vmx.c

2470

case MSR_IA32_CR_PAT:

arch/x86/kvm/vmx/vmx.c

4572

rdmsr(MSR_IA32_CR_PAT, low32, high32);

arch/x86/kvm/x86.c

10078

if (rdmsrq_safe(MSR_IA32_CR_PAT, &host_pat) ||

arch/x86/kvm/x86.c

338

MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,

arch/x86/kvm/x86.c

4025

case MSR_IA32_CR_PAT:

arch/x86/kvm/x86.c

4436

case MSR_IA32_CR_PAT:

arch/x86/mm/pat/memtype.c

236

wrmsrq(MSR_IA32_CR_PAT, pat_msr_val);

arch/x86/mm/pat/memtype.c

260

rdmsrq(MSR_IA32_CR_PAT, pat_msr_val);

tools/testing/selftests/kvm/lib/x86/svm.c

118

save->g_pat = rdmsr(MSR_IA32_CR_PAT);

tools/testing/selftests/kvm/lib/x86/vmx.c

273

vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT));

tools/testing/selftests/kvm/x86/msrs_test.c

358

MSR_TEST_NON_ZERO(MSR_IA32_CR_PAT, 0x07070707, 0, 0x7040600070406, NONE),