arch/x86/events/amd/core.c

1427

x86_pmu.perfctr = MSR_F15H_PERF_CTR;

arch/x86/include/asm/msr-index.h

831

#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR

arch/x86/include/asm/msr-index.h

832

#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)

arch/x86/include/asm/msr-index.h

833

#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)

arch/x86/include/asm/msr-index.h

834

#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)

arch/x86/include/asm/msr-index.h

835

#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)

arch/x86/include/asm/msr-index.h

836

#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)

arch/x86/kernel/cpu/perfctr-watchdog.c

51

if (msr >= MSR_F15H_PERF_CTR)

arch/x86/kernel/cpu/perfctr-watchdog.c

52

return (msr - MSR_F15H_PERF_CTR) >> 1;

arch/x86/kvm/svm/svm.c

750

svm_set_intercept_for_msr(vcpu, MSR_F15H_PERF_CTR + 2 * i,

arch/x86/kvm/svm/svm.c

754

svm_enable_intercept_for_msr(vcpu, MSR_F15H_PERF_CTR + 2 * i,

arch/x86/xen/pmu.c

119

return MSR_F15H_PERF_CTR + (addr - MSR_K7_PERFCTR0);

arch/x86/xen/pmu.c

139

msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) ||

arch/x86/xen/pmu.c

77

amd_counters_base = MSR_F15H_PERF_CTR;

tools/arch/x86/include/asm/msr-index.h

831

#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR

tools/arch/x86/include/asm/msr-index.h

832

#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)

tools/arch/x86/include/asm/msr-index.h

833

#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)

tools/arch/x86/include/asm/msr-index.h

834

#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)

tools/arch/x86/include/asm/msr-index.h

835

#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)

tools/arch/x86/include/asm/msr-index.h

836

#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)