MSR_AMD64_SEV_ES_GHCB
raw_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m);
raw_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m);
return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB);
native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
rdmsrq(MSR_AMD64_SEV_ES_GHCB, ghcb_gpa);
return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB);
native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val);
svm_disable_intercept_for_msr(vcpu, MSR_AMD64_SEV_ES_GHCB, MSR_TYPE_RW);
wrmsr(MSR_AMD64_SEV_ES_GHCB, GHCB_MSR_TERM_REQ);
wrmsr(MSR_AMD64_SEV_ES_GHCB, GHCB_MSR_TERM_REQ);