drivers/net/phy/mscc/mscc_ptp.c

307

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i),

drivers/net/phy/mscc/mscc_ptp.c

587

val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));

drivers/net/phy/mscc/mscc_ptp.c

590

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);

drivers/net/phy/mscc/mscc_ptp.c

956

val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));

drivers/net/phy/mscc/mscc_ptp.c

961

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);

drivers/net/phy/mscc/mscc_ptp.h

329

#define MSCC_ANA_IP1_FLOW_MATCH_UPPER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 1)

drivers/net/phy/mscc/mscc_ptp.h

330

#define MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 2)

drivers/net/phy/mscc/mscc_ptp.h

331

#define MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 3)

drivers/net/phy/mscc/mscc_ptp.h

332

#define MSCC_ANA_IP1_FLOW_MATCH_LOWER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 4)

drivers/net/phy/mscc/mscc_ptp.h

333

#define MSCC_ANA_IP1_FLOW_MASK_UPPER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 5)

drivers/net/phy/mscc/mscc_ptp.h

334

#define MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 6)

drivers/net/phy/mscc/mscc_ptp.h

335

#define MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 7)

drivers/net/phy/mscc/mscc_ptp.h

336

#define MSCC_ANA_IP1_FLOW_MASK_LOWER(x) (MSCC_ANA_IP1_FLOW_ENA(x) + 8)