drivers/net/phy/mscc/mscc_ptp.c

311

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i),

drivers/net/phy/mscc/mscc_ptp.c

550

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0),

drivers/net/phy/mscc/mscc_ptp.c

910

val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0));

drivers/net/phy/mscc/mscc_ptp.c

914

vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val);

drivers/net/phy/mscc/mscc_ptp.h

108

#define MSCC_ANA_ETH1_FLOW_VLAN_RANGE_I_TAG(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 4)

drivers/net/phy/mscc/mscc_ptp.h

109

#define MSCC_ANA_ETH1_FLOW_VLAN_TAG1(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 5)

drivers/net/phy/mscc/mscc_ptp.h

110

#define MSCC_ANA_ETH1_FLOW_VLAN_TAG2_I_TAG(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 6)

drivers/net/phy/mscc/mscc_ptp.h

90

#define MSCC_ANA_ETH1_FLOW_MATCH_MODE(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 1)

drivers/net/phy/mscc/mscc_ptp.h

96

#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 2)

drivers/net/phy/mscc/mscc_ptp.h

98

#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 3)