MSPI
bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
qspi->base[MSPI] = devm_ioremap_resource(dev, res);
if (IS_ERR(qspi->base[MSPI]))
return PTR_ERR(qspi->base[MSPI]);
rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
val = bcm_qspi_read(qspi, MSPI, offset);
msb = bcm_qspi_read(qspi, MSPI, msb_offset);
lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
bcm_qspi_write(qspi, MSPI, reg_offset, val);
bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);