ASS_CLK_DIV
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
{ ASS_CLK_DIV, 0 },
reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
{ASS_CLK_DIV, 0},