drivers/clk/mmp/clk-of-mmp2.c

106

{MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},

drivers/clk/mmp/clk-of-mmp2.c

111

{MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},

drivers/clk/spacemit/ccu-k1.c

44

CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,

drivers/clk/spacemit/ccu-k1.c

46

CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,

drivers/clk/spacemit/ccu-k1.c

48

CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,

drivers/clk/spacemit/ccu-k3.c

57

MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

59

MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

61

MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

63

MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

65

MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

67

MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

69

MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE);

drivers/clk/spacemit/ccu-k3.c

71

MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE);