drivers/accel/amdxdna/npu3_regs.c

29

#define NPU3_SMU_BAR_BASE MMNPU_APERTURE4_BASE

drivers/accel/amdxdna/npu3_regs.c

65

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu4_regs.c

186

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu4_regs.c

64

#define NPU4_SMU_BAR_BASE MMNPU_APERTURE4_BASE

drivers/accel/amdxdna/npu5_regs.c

62

#define NPU5_SMU_BAR_BASE MMNPU_APERTURE4_BASE

drivers/accel/amdxdna/npu5_regs.c

92

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU5_SMU, MMNPU_APERTURE4_BASE),

drivers/accel/amdxdna/npu6_regs.c

62

#define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE

drivers/accel/amdxdna/npu6_regs.c

92

DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE),