arch/powerpc/include/asm/book3s/64/hash-64k.h

171

(((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)

arch/powerpc/include/asm/book3s/64/mmu.h

172

if (psize == MMU_PAGE_64K)

arch/powerpc/include/asm/book3s/64/mmu.h

201

#define mmu_virtual_psize MMU_PAGE_64K

arch/powerpc/include/asm/book3s/64/tlbflush-radix.h

19

if (psize == MMU_PAGE_64K)

arch/powerpc/include/asm/nohash/32/mmu-44x.h

141

#define mmu_virtual_psize MMU_PAGE_64K

arch/powerpc/kvm/book3s_64_mmu.c

179

case MMU_PAGE_64K:

arch/powerpc/kvm/book3s_64_mmu.c

181

return MMU_PAGE_64K;

arch/powerpc/kvm/book3s_64_mmu.c

398

slbe->base_page_size = MMU_PAGE_64K;

arch/powerpc/kvm/book3s_64_mmu.c

579

int pagesize = MMU_PAGE_64K;

arch/powerpc/kvm/book3s_64_mmu.c

622

if (pagesize >= MMU_PAGE_64K &&

arch/powerpc/kvm/book3s_64_mmu.c

623

mmu_psize_defs[MMU_PAGE_64K].shift &&

arch/powerpc/kvm/book3s_64_mmu.c

96

case MMU_PAGE_64K:

arch/powerpc/kvm/book3s_64_mmu_host.c

143

hpsize = MMU_PAGE_64K;

arch/powerpc/kvm/book3s_64_mmu_host.c

345

slb_vsid |= mmu_psize_defs[MMU_PAGE_64K].sllp;

arch/powerpc/kvm/book3s_64_mmu_radix.c

1218

add_rmmu_ap_encoding(info, MMU_PAGE_64K, &i);

arch/powerpc/kvm/book3s_pr.c

707

pte.page_size = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_64k.c

102

flush_hash_page(vpn, rpte, MMU_PAGE_64K, ssize, flags);

arch/powerpc/mm/book3s64/hash_64k.c

237

unsigned long shift = mmu_psize_defs[MMU_PAGE_64K].shift;

arch/powerpc/mm/book3s64/hash_64k.c

283

if (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, MMU_PAGE_64K,

arch/powerpc/mm/book3s64/hash_64k.c

284

MMU_PAGE_64K, ssize,

arch/powerpc/mm/book3s64/hash_64k.c

299

MMU_PAGE_64K, MMU_PAGE_64K,

arch/powerpc/mm/book3s64/hash_64k.c

309

MMU_PAGE_64K,

arch/powerpc/mm/book3s64/hash_64k.c

310

MMU_PAGE_64K, ssize);

arch/powerpc/mm/book3s64/hash_64k.c

329

MMU_PAGE_64K, MMU_PAGE_64K, old_pte);

arch/powerpc/mm/book3s64/hash_hugepage.c

85

flush_hash_hugepage(vsid, ea, pmdp, MMU_PAGE_64K,

arch/powerpc/mm/book3s64/hash_pgtable.c

331

psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_pgtable.c

391

if (mmu_psize_defs[MMU_PAGE_64K].shift &&

arch/powerpc/mm/book3s64/hash_pgtable.c

392

(mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1))

arch/powerpc/mm/book3s64/hash_utils.c

1111

if (mmu_psize_defs[MMU_PAGE_64K].shift) {

arch/powerpc/mm/book3s64/hash_utils.c

1112

mmu_virtual_psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_utils.c

1113

mmu_vmalloc_psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_utils.c

1115

mmu_linear_psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_utils.c

1123

mmu_io_psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_utils.c

1870

if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {

arch/powerpc/mm/book3s64/hash_utils.c

1879

if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {

arch/powerpc/mm/book3s64/hash_utils.c

1905

if (psize == MMU_PAGE_64K)

arch/powerpc/mm/book3s64/hash_utils.c

2093

if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)

arch/powerpc/mm/book3s64/hash_utils.c

831

idx = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/hash_utils.c

893

if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)

arch/powerpc/mm/book3s64/pgtable.c

523

atomic_long_read(&direct_pages_count[MMU_PAGE_64K]) << 6);

arch/powerpc/mm/book3s64/radix_pgtable.c

513

idx = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/radix_pgtable.c

587

mmu_psize_defs[MMU_PAGE_64K].shift = 16;

arch/powerpc/mm/book3s64/radix_pgtable.c

588

mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;

arch/powerpc/mm/book3s64/radix_pgtable.c

589

mmu_psize_defs[MMU_PAGE_64K].h_rpt_pgsize =

arch/powerpc/mm/book3s64/radix_pgtable.c

590

psize_to_rpti_pgsize(MMU_PAGE_64K);

arch/powerpc/mm/book3s64/radix_pgtable.c

602

mmu_virtual_psize = MMU_PAGE_64K;

arch/powerpc/mm/book3s64/radix_tlb.c

1450

__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),

arch/powerpc/mm/book3s64/radix_tlb.c

250

__tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);

arch/powerpc/mm/book3s64/radix_tlb.c

283

__tlbie_lpid_va(va, lpid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);

arch/powerpc/mm/book3s64/slice.c

420

#define MMU_PAGE_BASE MMU_PAGE_64K

arch/powerpc/mm/book3s64/slice.c

514

if (IS_ENABLED(CONFIG_PPC_64K_PAGES) && psize == MMU_PAGE_64K) {

arch/powerpc/mm/book3s64/slice.c

593

psize == MMU_PAGE_64K) {

arch/powerpc/mm/book3s64/slice.c

799

if (IS_ENABLED(CONFIG_PPC_64K_PAGES) && psize == MMU_PAGE_64K) {

arch/powerpc/platforms/cell/spu_base.c

117

return mmu_psize_defs[MMU_PAGE_64K].shift != 0;