drivers/accel/habanalabs/gaudi2/gaudi2.c

9365

valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9370

val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9373

addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9386

WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9394

valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9399

val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9402

addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9409

WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

285

#define MMU_BYPASS_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

286

#define MMU_SPI_SEI_MASK_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

287

#define MMU_SPI_SEI_CAUSE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

288

#define MMU_ENABLE_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

289

#define MMU_DDR_RANGE_REG_ENABLE MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

290

#define MMU_RR_SEC_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

291

#define MMU_RR_SEC_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

292

#define MMU_RR_SEC_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

293

#define MMU_RR_SEC_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

294

#define MMU_RR_PRIV_MIN_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

295

#define MMU_RR_PRIV_MIN_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

296

#define MMU_RR_PRIV_MAX_63_32_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

297

#define MMU_RR_PRIV_MAX_31_0_0_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0)

drivers/accel/habanalabs/include/gaudi2/asic_reg/gaudi2_regs.h

298

#define MMU_INTERRUPT_CLR_OFFSET MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR)