drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

490

MMSCH_V5_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

492

MMSCH_V5_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr));

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

494

MMSCH_V5_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4);

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

836

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

840

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

845

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

848

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

851

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

855

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

860

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

865

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

867

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

869

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

871

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

877

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

880

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

883

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

886

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

902

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

905

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c

908

MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,