MMCIMASK0
writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
u32 mask = readl_relaxed(base + MMCIMASK0);
writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);
writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0);
status &= readl(host->base + MMCIMASK0);
host->base + MMCIMASK0);
writel(0, host->base + MMCIMASK0);
writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
writel(0, host->base + MMCIMASK0);
writel(0, host->base + MMCIMASK0);
host->base + MMCIMASK0);
writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
host->base + MMCIMASK0);
unsigned int mask0 = readl(base + MMCIMASK0);
writel(mask0, base + MMCIMASK0);
writel(readl(base + MMCIMASK0) &
~host->variant->busy_detect_mask, base + MMCIMASK0);
writel(readl(base + MMCIMASK0) |
base + MMCIMASK0);
host->base + MMCIMASK0);
mask = readl_relaxed(base + MMCIMASK0);
base + MMCIMASK0);
base + MMCIMASK0);