MLX5_MAX_PORTS
struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
DECLARE_BITMAP(peer_used, MLX5_MAX_PORTS); /* tracks populated peer
struct list_head peer[MLX5_MAX_PORTS]; /* flows with peer flow */
static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
for_each_set_bit(i, flow->peer_used, MLX5_MAX_PORTS)
struct list_head peer_flows[MLX5_MAX_PORTS];
count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
for (i = 0; i < MLX5_MAX_PORTS; i++)
u8 ports[MLX5_MAX_PORTS] = {};
if (i < MLX5_MAX_PORTS) {
struct mlx5_core_dev *devs[MLX5_MAX_PORTS];
if (i < MLX5_MAX_PORTS) {
if (i < MLX5_MAX_PORTS) {
err = xa_alloc(&ldev->pfs, &idx, pf, XA_LIMIT(0, MLX5_MAX_PORTS - 1),
if (i >= MLX5_MAX_PORTS)
char buf[MLX5_MAX_PORTS * 10 + 1] = {};
u8 enabled_ports[MLX5_MAX_PORTS] = {};
return MLX5_MAX_PORTS;
return MLX5_MAX_PORTS;
if (*i == MLX5_MAX_PORTS)
if (idx == MLX5_MAX_PORTS) {
mdev = kvzalloc(sizeof(mdev[0]) * MLX5_MAX_PORTS, GFP_KERNEL);
int disabled[MLX5_MAX_PORTS] = {};
int enabled[MLX5_MAX_PORTS] = {};
u8 enabled_ports[MLX5_MAX_PORTS] = {};
u8 disabled_ports[MLX5_MAX_PORTS] = {};
u8 ports[MLX5_MAX_PORTS * MLX5_LAG_MAX_HASH_BUCKETS] = {};
mlx5_get_dev_index(dev) >= MLX5_MAX_PORTS ||
MLX5_CAP_GEN(dev, num_lag_ports) > MLX5_MAX_PORTS)
i = tmp, tmp < MLX5_MAX_PORTS; tmp++)
struct netdev_lag_lower_state_info netdev_state[MLX5_MAX_PORTS];
u8 v2p_map[MLX5_MAX_PORTS * MLX5_LAG_MAX_HASH_BUCKETS];
mlx5_ldev_for_each_reverse(i, MLX5_MAX_PORTS, 0, ldev) {
u32 pf_metadata[MLX5_MAX_PORTS];
struct mlx5_flow_handle *rules[MLX5_MAX_PORTS * MLX5_LAG_MAX_HASH_BUCKETS];
if (idx >= 1 && idx <= MLX5_MAX_PORTS)
u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];