MLX5_GET64
MLX5_GET64(modify_memic_out, out, memic_operation_addr);
MLX5_GET64(alloc_memic_out, out, memic_start_addr);
MLX5_GET64(ib_ext_port_cntrs_grp_data_layout, \
(MLX5_GET64(query_vport_counter_out, p, cntr1) + \
MLX5_GET64(query_vport_counter_out, p, cntr2))
offset = io_virt - MLX5_GET64(query_mkey_out, out,
MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
in->db_record = MLX5_GET64(wq, wq, dbr_addr);
in->db_record = MLX5_GET64(srqc, srqc, dbr_addr);
icm_rx = MLX5_GET64(
icm_tx = MLX5_GET64(
MLX5_GET64(query_vnic_env_out, (vnic_env_stats)->query_vnic_env_out, \
*clock_id = MLX5_GET64(msecq_reg, out, local_clock_identity);
modify_field_select = MLX5_GET64(ipsec_obj, obj, modify_field_select);
modify_field_select = MLX5_GET64(macsec_offload_obj, obj, modify_field_select);
MLX5_GET64(query_vport_counter_out, p, x)
hist->values[i].sum = MLX5_GET64(rs_histogram_cntrs,
#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
MLX5_GET64(ppcnt_reg, (pstats)->phy_recovery_counters, \
MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
MLX5_GET64(query_vport_counter_out, p, x)
data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,
*packets = MLX5_GET64(traffic_counter, stats, packets);
*bytes = MLX5_GET64(traffic_counter, stats, octets);
u64 packets = MLX5_GET64(traffic_counter, stats, packets);
u64 bytes = MLX5_GET64(traffic_counter, stats, octets);
mlx5_hwmon_init_sensors_indexes(hwmon, MLX5_GET64(mtcap_reg, mtcap_out, sensor_map));
host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp);
*device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp);
free_4k(dev, MLX5_GET64(manage_pages_in, in, pas[i]), function);
free_4k(dev, MLX5_GET64(manage_pages_out, out, pas[i]), function);
*icm_addr_0 = MLX5_GET64(flow_table_context, ft_ctx, sws.sw_owner_icm_root_0);
*icm_addr_1 = MLX5_GET64(flow_table_context, ft_ctx, sws.sw_owner_icm_root_1);
MLX5_GET64(query_hca_cap_out, out,
MLX5_GET64(fte_match_param, match_param, hdr)
output->sw_owner_icm_root_1 = MLX5_GET64(query_flow_table_out, out,
output->sw_owner_icm_root_0 = MLX5_GET64(query_flow_table_out, out,
MLX5_GET64(query_esw_vport_context_out, out,
*rx_icm_addr = MLX5_GET64(sampler_obj, attr,
*tx_icm_addr = MLX5_GET64(sampler_obj, attr,
MLX5_GET64(query_esw_vport_context_out, out,
*rx_discard_vport_down = MLX5_GET64(query_vnic_env_out, out,
*tx_discard_vport_down = MLX5_GET64(query_vnic_env_out, out,
*system_image_guid = MLX5_GET64(query_nic_vport_context_out, out,
*node_guid = MLX5_GET64(query_nic_vport_context_out, out,
*received_desc = MLX5_GET64(virtio_q_counters, ctx, received_desc);
*completed_desc = MLX5_GET64(virtio_q_counters, ctx, completed_desc);
MLX5_GET64(query_vhca_migration_state_out, out,
u64 ___t = MLX5_GET64(typ, p, fld); \
MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
MLX5_GET64(flow_table_eswitch_cap, \
MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
MLX5_GET64(virtio_emulation_cap, \