MLX5_CAP_QOS
if (MLX5_CAP_QOS(mdev, packet_pacing) &&
MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
MLX5_CAP_QOS(dev->mdev, packet_pacing) &&
MLX5_CAP_QOS(dev->mdev, packet_pacing_uid));
MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
MLX5_CAP_QOS(mdev, log_meter_aso_max_alloc));
max_level = 1 << MLX5_CAP_QOS(node->esw->dev, log_esw_max_sched_depth);
max_level = 1 << MLX5_CAP_QOS(node->esw->dev, log_esw_max_sched_depth);
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
if (bw_share && (!MLX5_CAP_QOS(dev, esw_bw_share) ||
MLX5_CAP_QOS(dev, max_tsar_bw_share) < MLX5_MIN_BW_SHARE))
u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share);
u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share);
fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share);
if (!MLX5_CAP_QOS(esw->dev, log_esw_max_sched_depth))
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
max_level = 1 << MLX5_CAP_QOS(vport_node->esw->dev,
err = mlx5_core_get_caps_mode(dev, MLX5_CAP_QOS, HCA_CAP_OPMOD_GET_CUR);
MLX5_CAP_QOS,
if (!MLX5_CAP_QOS(mdev, nic_sq_scheduling))
if (!MLX5_CAP_QOS(mdev, nic_bw_share))
if (!MLX5_CAP_QOS(mdev, nic_rate_limit))
return 1 << MLX5_CAP_QOS(mdev, log_max_qos_nic_queue_group);
MLX5_CAP_QOS(dev, packet_pacing_uid) ?
MLX5_CAP_QOS(dev, packet_pacing_uid) ?
cap = MLX5_CAP_QOS(dev, esw_tsar_type);
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing))
cap = MLX5_CAP_QOS(dev, nic_tsar_type);
cap = MLX5_CAP_QOS(dev, esw_element_type);
cap = MLX5_CAP_QOS(dev, nic_element_type);
MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)