MLX5_CAP_ETH
if (MLX5_CAP_ETH(mdev, csum_cap)) {
if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
if (MLX5_CAP_ETH(mdev, swp)) {
if (MLX5_CAP_ETH(mdev, swp_csum))
if (MLX5_CAP_ETH(mdev, swp_lso))
if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
MLX5_CAP_ETH(dev->mdev, swp))
cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) ||
MLX5_CAP_ETH(mdev, tunnel_stateless_gre) ||
MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx);
MLX5_CAP_ETH(mdev, scatter_fcs);
MLX5_CAP_ETH(mdev, vlan_cap);
if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
if (!MLX5_CAP_ETH(dev, self_lb_en_modifiable))
if (!MLX5_CAP_ETH(dev, csum_cap)) {
if (!MLX5_CAP_ETH(dev, max_lso_cap)) {
if (!MLX5_CAP_ETH(dev, vlan_cap)) {
if (!MLX5_CAP_ETH(dev, rss_ind_tbl_cap)) {
return MLX5_CAP_ETH(mdev, swp) &&
MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq));
MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq));
if (!MLX5_CAP_ETH(priv->mdev, tunnel_stateless_mpls_over_udp) &&
if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial) || !skb_is_gso(skb))
if (!MLX5_CAP_ETH(mdev, swp_csum)) {
if (!MLX5_CAP_ETH(mdev, swp_lso)) {
MLX5_CAP_ETH(mdev, insert_trailer) && MLX5_CAP_ETH(mdev, swp))
if (!MLX5_CAP_ETH(mdev, swp)) {
if (!MLX5_CAP_ETH(mdev, swp_csum)) {
if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial)) {
if (!MLX5_CAP_ETH(mdev, swp_lso)) {
MLX5_CAP_ETH(mdev, reg_umr_sq);
if (MLX5_CAP_ETH(mdev, cqe_checksum_full))
if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx));
return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre);
if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
!MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) &&
!MLX5_CAP_ETH(mdev, tunnel_lro_gre) &&
if (MLX5_CAP_ETH(mdev, scatter_fcs))
switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
return MLX5_CAP_ETH(mdev, tunnel_stateless_gre);
return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) ||
MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_rx));
if (!MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || !mlx5_core_is_pf(mdev))
return MLX5_CAP_ETH(mdev, max_vxlan_udp_ports) ?: 4;
switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {