drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c

1674

*cmd++ = MI_LOAD_REGISTER_MEM;

drivers/gpu/drm/i915/gt/selftest_workarounds.c

564

lrm = MI_LOAD_REGISTER_MEM;

drivers/gpu/drm/i915/i915_cmd_parser.c

1280

if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {

drivers/gpu/drm/i915/i915_cmd_parser.c

238

CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,

drivers/gpu/drm/i915/i915_perf.c

1921

cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;

drivers/gpu/drm/xe/xe_lrc.c

1114

*cmd++ = MI_LOAD_REGISTER_MEM | MI_LRM_USE_GGTT | MI_LRI_LRM_CS_MMIO |

drivers/gpu/drm/xe/xe_lrc.c

1120

*cmd++ = MI_LOAD_REGISTER_MEM | MI_LRM_USE_GGTT | MI_LRI_LRM_CS_MMIO |

drivers/gpu/drm/xe/xe_lrc.c

1126

*cmd++ = MI_LOAD_REGISTER_MEM | MI_LRM_USE_GGTT | MI_LRI_LRM_CS_MMIO;

drivers/gpu/drm/xe/xe_lrc.c

1904

case MI_LOAD_REGISTER_MEM & MI_OPCODE:

drivers/gpu/drm/xe/xe_lrc.c

657

regs[CTX_LRM_INT_MASK_ENABLE] = MI_LOAD_REGISTER_MEM |