drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

2222

*cs++ = MI_LOAD_REGISTER_IMM(4);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

165

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

205

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/gen7_renderclear.c

399

batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

209

*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2750

*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;

drivers/gpu/drm/i915/gt/intel_lrc.c

1335

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_lrc.c

1345

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_lrc.c

1648

*batch++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_lrc.c

1723

*batch++ = MI_LOAD_REGISTER_IMM(count);

drivers/gpu/drm/i915/gt/intel_lrc.c

77

*regs = MI_LOAD_REGISTER_IMM(count);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

704

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

708

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

718

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

762

*cs++ = MI_LOAD_REGISTER_IMM(num_engines);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

816

*cs++ = MI_LOAD_REGISTER_IMM(num_engines);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

862

*cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1023

*cs++ = MI_LOAD_REGISTER_IMM(wal->count);

drivers/gpu/drm/i915/gt/selftest_execlists.c

3083

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/selftest_execlists.c

4250

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/selftest_lrc.c

1196

*cs++ = MI_LOAD_REGISTER_IMM(len);

drivers/gpu/drm/i915/gt/selftest_lrc.c

549

*cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW);

drivers/gpu/drm/i915/gt/selftest_rps.c

101

*cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2);

drivers/gpu/drm/i915/gt/selftest_rps.c

109

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

580

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

593

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/gt/selftest_workarounds.c

904

*cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine));

drivers/gpu/drm/i915/gvt/mmio_context.c

234

*cs++ = MI_LOAD_REGISTER_IMM(count);

drivers/gpu/drm/i915/gvt/mmio_context.c

267

*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);

drivers/gpu/drm/i915/gvt/mmio_context.c

294

*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);

drivers/gpu/drm/i915/i915_cmd_parser.c

1292

if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&

drivers/gpu/drm/i915/i915_cmd_parser.c

229

CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_cmd_parser.c

486

CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,

drivers/gpu/drm/i915/i915_perf.c

2024

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/i915_perf.c

2042

*cs++ = MI_LOAD_REGISTER_IMM(1);

drivers/gpu/drm/i915/i915_perf.c

2090

*cs++ = MI_LOAD_REGISTER_IMM(2);

drivers/gpu/drm/i915/i915_perf.c

2171

*cs++ = MI_LOAD_REGISTER_IMM(n_lri);

drivers/gpu/drm/i915/i915_perf.c

2520

*cs++ = MI_LOAD_REGISTER_IMM(count);

drivers/gpu/drm/i915/selftests/i915_perf.c

342

*cs++ = MI_LOAD_REGISTER_IMM(32);

drivers/gpu/drm/xe/xe_configfs.c

735

MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1));

drivers/gpu/drm/xe/xe_gt.c

282

*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);

drivers/gpu/drm/xe/xe_gt.c

313

*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);

drivers/gpu/drm/xe/xe_gt.c

324

*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |

drivers/gpu/drm/xe/xe_gt.c

351

*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) |

drivers/gpu/drm/xe/xe_gt.c

362

*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);

drivers/gpu/drm/xe/xe_lrc.c

1205

*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);

drivers/gpu/drm/xe/xe_lrc.c

1897

case MI_LOAD_REGISTER_IMM:

drivers/gpu/drm/xe/xe_lrc.c

202

*regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);

drivers/gpu/drm/xe/xe_lrc.c

663

regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(num_regs) |

drivers/gpu/drm/xe/xe_oa.c

680

bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(n_lri);

drivers/gpu/drm/xe/xe_ring_ops.c

54

dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;