drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

214

cmd = MI_FLUSH_DW;

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

186

cmd = MI_FLUSH_DW;

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

380

*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

400

*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

411

*cs++ = MI_FLUSH_DW;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

383

cmd = MI_FLUSH_DW + 1;

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

89

cmd = MI_FLUSH_DW + 1;

drivers/gpu/drm/i915/gt/gen8_engine_cs.h

120

*cs++ = (MI_FLUSH_DW + 1) | flags;

drivers/gpu/drm/i915/gt/intel_migrate.c

523

*cmd++ = MI_FLUSH_DW | flags;

drivers/gpu/drm/i915/i915_cmd_parser.c

347

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

391

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

428

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,

drivers/gpu/drm/i915/i915_cmd_parser.c

491

CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),

drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c

28

*cs++ = MI_FLUSH_DW;

drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c

38

*cs++ = MI_FLUSH_DW | MI_FLUSH_DW_PROTECTED_MEM_EN |

drivers/gpu/drm/xe/xe_migrate.c

1072

dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW |

drivers/gpu/drm/xe/xe_pxp_submit.c

248

emit_cmd(xe, batch, offset++, MI_FLUSH_DW | MI_FLUSH_IMM_DW);

drivers/gpu/drm/xe/xe_pxp_submit.c

260

emit_cmd(xe, batch, offset++, MI_FLUSH_DW |

drivers/gpu/drm/xe/xe_ring_ops.c

113

dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW |

drivers/gpu/drm/xe/xe_ring_ops.c

83

dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;

drivers/gpu/drm/xe/xe_ring_ops.c

93

dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |