drivers/gpu/drm/i915/gt/gen2_engine_cs.c

244

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

264

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

drivers/gpu/drm/i915/gt/gen2_engine_cs.c

286

*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security;

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

469

*cs++ = MI_BATCH_BUFFER_START | flags;

drivers/gpu/drm/i915/gt/selftest_hangcheck.c

183

*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;

drivers/gpu/drm/i915/gt/selftest_hangcheck.c

197

*batch++ = MI_BATCH_BUFFER_START | 1 << 8;

drivers/gpu/drm/i915/gt/selftest_hangcheck.c

210

*batch++ = MI_BATCH_BUFFER_START | 2 << 6;

drivers/gpu/drm/i915/gt/selftest_hangcheck.c

222

*batch++ = MI_BATCH_BUFFER_START | 2 << 6;

drivers/gpu/drm/i915/gt/selftest_tlb.c

118

*cs++ = MI_BATCH_BUFFER_START | BIT(8) | 1;

drivers/gpu/drm/i915/i915_cmd_parser.c

1515

if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {

drivers/gpu/drm/i915/i915_cmd_parser.c

250

CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),

drivers/gpu/drm/i915/i915_perf.c

2074

MI_BATCH_BUFFER_START :

drivers/gpu/drm/i915/i915_perf.c

2117

MI_BATCH_BUFFER_START :

drivers/gpu/drm/i915/i915_perf.c

2243

MI_BATCH_BUFFER_START :

drivers/gpu/drm/i915/selftests/i915_request.c

1148

*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;

drivers/gpu/drm/i915/selftests/i915_request.c

1152

*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;

drivers/gpu/drm/i915/selftests/i915_request.c

1155

*cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

drivers/gpu/drm/i915/selftests/igt_spinner.c

187

*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;

drivers/gpu/drm/i915/selftests/igt_spinner.c

189

*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;

drivers/gpu/drm/i915/selftests/igt_spinner.c

191

*batch++ = MI_BATCH_BUFFER_START;

drivers/gpu/drm/i915/selftests/igt_spinner.c

193

*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;

drivers/gpu/drm/xe/xe_ring_ops.c

104

dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);

drivers/gpu/drm/xe/xe_sriov_vf_ccs.c

194

dw[i++] = MI_BATCH_BUFFER_START | XE_INSTR_NUM_DW(3);