arch/powerpc/perf/isa207-common.h

276

#define PM(a, b) (P(LVL, MISS) | P(a, b))

arch/x86/events/intel/ds.c

122

#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))

arch/x86/events/intel/ds.c

126

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */

arch/x86/events/intel/ds.c

131

OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */

arch/x86/events/intel/ds.c

234

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* 0x00: ukn L3 */

arch/x86/events/intel/ds.c

249

P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x0f: L3 Miss Snoop HitM */

arch/x86/events/intel/ds.c

280

OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x09: Prefetch Promotion */

arch/x86/events/intel/ds.c

281

OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x0a: Cross Core Prefetch Promotion */

arch/x86/events/intel/ds.c

356

val |= P(SNOOP, MISS);

arch/x86/events/intel/ds.c

386

val |= P(TLB, MISS);

arch/x86/events/intel/ds.c

398

val |= P(LVL, MISS);

arch/x86/events/intel/ds.c

445

*val |= P(TLB, MISS) | P(TLB, L2);

arch/x86/events/intel/ds.c

516

val |= P(TLB, MISS) | P(TLB, L2);

arch/x86/events/intel/ds.c

551

val |= P(TLB, MISS) | P(TLB, L2);

arch/x86/events/intel/ds.c

609

val |= P(TLB, MISS) | P(TLB, L2);

arch/x86/events/intel/p4.c

100

P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, MISS) |

arch/x86/events/intel/p4.c

551

[ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,

drivers/net/ethernet/amd/ariadne.c

285

if (csr0 & MISS)

drivers/net/ethernet/amd/ariadne.c

368

if (csr0 & MISS) {

drivers/net/ethernet/amd/ariadne.c

383

lance->RDP = INEA | BABL | CERR | MISS | MERR | IDON;

tools/perf/util/intel-pt.c

2281

#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))

tools/perf/util/intel-pt.c

2288

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss|SNP N/A */

tools/perf/util/intel-pt.c

2308

P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA), /* L3 miss|SNP N/A */

tools/perf/util/intel-pt.c

2313

OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* L3 hit|SNP Hit */

tools/perf/util/intel-pt.c

2335

*val |= P(TLB, MISS) | P(TLB, L2);

tools/perf/util/mem-events.c

733

if ((lvl & P(LVL, MISS)))

tools/perf/util/mem-events.c

749

if (lvl & P(LVL, MISS))