MISC
ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0);
ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4);
ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
ivpu_dbg(vdev, MISC, "MSR_INTEGRITY_CAPS: 0x%llx\n", msr_integrity_caps);
ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", platform_to_str(platform), platform);
ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);
ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",
MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
#define MISC_CFG_FW_CTRL (MISC + 0x000000001000)
#define MISC_CFG_RSA_CMD (MISC + 0x000000000A08)
#define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400)
#define MISC_CFG_RSA_MU (MISC + 0x000000000A10)
#define MISC_CFG_RSA_R2 (MISC + 0x000000000000)
#define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200)
#define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00)
#define MISC_ERR_CLEAR (MISC + 0x000000002010)
#define MISC_ERR_MASK (MISC + 0x000000002008)
#define MISC_ERR_STATUS (MISC + 0x000000002000)
case MISC:
MT6357_TOP_GEN(MISC),
MT6358_TOP_GEN(MISC),
MT6359_TOP_GEN(MISC),
BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
misc = readw(ctrl->hpc_reg + MISC);
writew(misc, ctrl->hpc_reg + MISC);
misc = readw(ctrl->hpc_reg + MISC);
temp_word = readw(ctrl->hpc_reg + MISC);
writew(temp_word, ctrl->hpc_reg + MISC);
misc = readw(ctrl->hpc_reg + MISC);
writew(misc, ctrl->hpc_reg + MISC);
misc = readw(ctrl->hpc_reg + MISC);
writew(misc, ctrl->hpc_reg + MISC);
misc = readw(ctrl->hpc_reg + MISC);
unsigned char MISC;
Miscdata = SiS_Pr->SiS_StandTable[StandTableIndex].MISC;
unsigned char MISC;
if (PRINT_FIELD(MISC)) {