arch/mips/alchemy/common/irq.c

1003

do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));

arch/mips/alchemy/common/irq.c

925

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch);

arch/mips/alchemy/common/irq.c

926

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch);

arch/mips/alchemy/common/irq.c

927

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch);

arch/mips/alchemy/common/irq.c

928

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch);

arch/mips/alchemy/common/irq.c

965

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch);

arch/mips/alchemy/common/irq.c

966

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch);

arch/mips/alchemy/common/irq.c

967

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch);

arch/mips/alchemy/common/irq.c

968

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch);

arch/mips/ath25/ar2315_regs.h

20

#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */

arch/mips/ath25/ar2315_regs.h

21

#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */

arch/mips/ath25/ar2315_regs.h

22

#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */

arch/mips/ath25/ar2315_regs.h

23

#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */

arch/mips/ath25/ar2315_regs.h

24

#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */

arch/mips/ath25/ar5312_regs.h

17

#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */

arch/mips/ath25/ar5312_regs.h

18

#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */

arch/mips/ath25/ar5312_regs.h

19

#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */

arch/mips/ath25/ar5312_regs.h

20

#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */

arch/mips/ath25/ar5312_regs.h

21

#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */

arch/mips/ath25/devices.h

9

#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */

arch/mips/bcm63xx/irq.c

528

irq = MIPS_CPU_IRQ_BASE + i;

arch/mips/bcm63xx/irq.c

537

irq = MIPS_CPU_IRQ_BASE + 2;

arch/mips/bcm63xx/irq.c

542

irq = MIPS_CPU_IRQ_BASE + 3;

arch/mips/cavium-octeon/octeon-irq.c

2981

do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);

arch/mips/cobalt/irq.c

37

do_IRQ(MIPS_CPU_IRQ_BASE + 3);

arch/mips/cobalt/irq.c

39

do_IRQ(MIPS_CPU_IRQ_BASE + 4);

arch/mips/cobalt/irq.c

41

do_IRQ(MIPS_CPU_IRQ_BASE + 5);

arch/mips/cobalt/irq.c

43

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/generic/irq.c

26

mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

arch/mips/generic/irq.c

42

mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;

arch/mips/generic/irq.c

58

mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

arch/mips/include/asm/dec/interrupts.h

91

#define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */

arch/mips/include/asm/ip32/ip32_ints.h

25

CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,

arch/mips/include/asm/jazz.h

206

#define JAZZ_TIMER_IRQ (MIPS_CPU_IRQ_BASE+6)

arch/mips/include/asm/mach-ath79/irq.h

12

#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))

arch/mips/include/asm/mach-au1x00/au1000.h

39

#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)

arch/mips/include/asm/mach-au1x00/au1000.h

46

#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)

arch/mips/include/asm/mach-cobalt/irq.h

42

#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)

arch/mips/include/asm/mach-cobalt/irq.h

43

#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)

arch/mips/include/asm/mach-cobalt/irq.h

44

#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)

arch/mips/include/asm/mach-cobalt/irq.h

45

#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)

arch/mips/include/asm/mach-cobalt/irq.h

46

#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)

arch/mips/include/asm/mach-cobalt/irq.h

47

#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)

arch/mips/include/asm/mach-cobalt/irq.h

48

#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)

arch/mips/include/asm/mach-cobalt/irq.h

49

#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)

arch/mips/include/asm/mach-db1x00/irq.h

16

#ifndef MIPS_CPU_IRQ_BASE

arch/mips/include/asm/mach-generic/irq.h

23

#ifndef MIPS_CPU_IRQ_BASE

arch/mips/include/asm/mach-ip27/irq.h

17

#define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2)

arch/mips/include/asm/mach-ip27/irq.h

18

#define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3)

arch/mips/include/asm/mach-ip27/irq.h

19

#define IP27_RT_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 4)

arch/mips/include/asm/mach-ip27/irq.h

21

#define IP27_HUB_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)

arch/mips/include/asm/sgi/ip22.h

28

#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */

arch/mips/include/asm/sni.h

146

#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE

arch/mips/include/asm/sni.h

154

#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)

arch/mips/include/asm/sni.h

179

#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)

arch/mips/include/asm/txx9irq.h

15

#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)

arch/mips/kernel/cevt-r4k.c

236

return MIPS_CPU_IRQ_BASE + cp0_compare_irq;

arch/mips/kernel/perf_event_mipsxx.c

1910

irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;

arch/mips/kernel/rtlx-mt.c

26

do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ);

arch/mips/kernel/rtlx-mt.c

54

static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ;

arch/mips/kernel/smp-bmips.c

69

#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)

arch/mips/kernel/smp-bmips.c

70

#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)

arch/mips/loongson2ef/common/serial.c

33

.irq = MIPS_CPU_IRQ_BASE + (int), \

arch/mips/loongson2ef/fuloong-2e/irq.c

27

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/loongson2ef/fuloong-2e/irq.c

58

irq = MIPS_CPU_IRQ_BASE + 2;

arch/mips/loongson2ef/fuloong-2e/irq.c

62

irq = MIPS_CPU_IRQ_BASE + 5;

arch/mips/loongson2ef/lemote-2f/irq.c

18

#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */

arch/mips/loongson2ef/lemote-2f/irq.c

19

#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */

arch/mips/loongson2ef/lemote-2f/irq.c

20

#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */

arch/mips/loongson2ef/lemote-2f/irq.c

21

#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */

arch/mips/loongson64/smp.c

29

#define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6)

arch/mips/mti-malta/malta-int.c

212

corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;

arch/mips/mti-malta/malta-int.c

217

corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;

arch/mips/mti-malta/malta-platform.c

48

.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,

arch/mips/mti-malta/malta-time.c

143

return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

arch/mips/mti-malta/malta-time.c

156

mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;

arch/mips/mti-malta/malta-time.c

173

mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;

arch/mips/n64/init.c

25

#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))

arch/mips/ralink/irq.c

24

#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)

arch/mips/ralink/irq.c

25

#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)

arch/mips/ralink/irq.c

26

#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)

arch/mips/ralink/irq.c

27

#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)

arch/mips/ralink/irq.c

28

#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)

arch/mips/sgi-ip30/ip30-common.h

13

#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)

arch/mips/sgi-ip30/ip30-common.h

14

#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)

arch/mips/sgi-ip30/ip30-common.h

15

#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)

arch/mips/sgi-ip30/ip30-common.h

16

#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)

arch/mips/sgi-ip30/ip30-common.h

17

#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)

arch/mips/sgi-ip32/ip32-irq.c

403

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/sibyte/sb1250/irq.c

305

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/sni/pcimt.c

281

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/sni/pcimt.c

283

do_IRQ(MIPS_CPU_IRQ_BASE + 6);

arch/mips/sni/pcit.c

214

do_IRQ(MIPS_CPU_IRQ_BASE + 4);

arch/mips/sni/pcit.c

216

do_IRQ(MIPS_CPU_IRQ_BASE + 5);

arch/mips/sni/pcit.c

218

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/sni/pcit.c

228

do_IRQ(MIPS_CPU_IRQ_BASE + 3);

arch/mips/sni/pcit.c

230

do_IRQ(MIPS_CPU_IRQ_BASE + 4);

arch/mips/sni/pcit.c

232

do_IRQ(MIPS_CPU_IRQ_BASE + 5);

arch/mips/sni/pcit.c

234

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/sni/pcit.c

262

if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",

arch/mips/sni/rm200.c

449

do_IRQ(MIPS_CPU_IRQ_BASE + 7);

arch/mips/txx9/generic/irq_tx4927.c

38

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,

arch/mips/txx9/generic/irq_tx4938.c

26

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,

arch/mips/txx9/rbtx4927/irq.c

177

irq = MIPS_CPU_IRQ_BASE + 7;

arch/mips/txx9/rbtx4927/irq.c

183

irq = MIPS_CPU_IRQ_BASE + 0;

arch/mips/txx9/rbtx4927/irq.c

185

irq = MIPS_CPU_IRQ_BASE + 1;

drivers/irqchip/irq-ath79-cpu.c

51

do_IRQ(MIPS_CPU_IRQ_BASE + irq);

drivers/irqchip/irq-mips-cpu.c

261

irq_domain = irq_domain_create_legacy(of_fwnode_handle(of_node), 8, MIPS_CPU_IRQ_BASE, 0,

drivers/irqchip/irq-mips-gic.c

207

return MIPS_CPU_IRQ_BASE + cp0_compare_irq;

drivers/irqchip/irq-mips-gic.c

218

return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;

drivers/irqchip/irq-mips-gic.c

230

return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;

drivers/irqchip/irq-mips-gic.c

966

irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,