MIPSInst_RT
regs->regs[MIPSInst_RT(ir)];
if (MIPSInst_RT(inst)) {
(s32)(((u32)regs->regs[MIPSInst_RT(ir)]) <<
rt = regs->regs[MIPSInst_RT(inst)];
(s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >>
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = rt;
rt = regs->regs[MIPSInst_RT(inst)];
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = rt;
(u32)regs->regs[MIPSInst_RT(ir)]);
rt = regs->regs[MIPSInst_RT(inst)];
rt = regs->regs[MIPSInst_RT(inst)];
(u32)regs->regs[MIPSInst_RT(ir)]);
rt = regs->regs[MIPSInst_RT(inst)];
(s64)(((u64)regs->regs[MIPSInst_RT(ir)]) <<
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = rt;
(s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >>
rt = regs->regs[MIPSInst_RT(inst)];
(u64)regs->regs[MIPSInst_RT(ir)];
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = rt;
rt = regs->regs[MIPSInst_RT(inst)];
(u64)regs->regs[MIPSInst_RT(ir)]);
rt = regs->regs[MIPSInst_RT(inst)];
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = res;
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
res = regs->regs[MIPSInst_RT(inst)];
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = res;
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = res;
res = regs->regs[MIPSInst_RT(inst)];
if (MIPSInst_RT(inst) && !err)
regs->regs[MIPSInst_RT(inst)] = res;
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
rt = regs->regs[MIPSInst_RT(ir)];
if (MIPSInst_RT(ir))
regs->regs[MIPSInst_RT(ir)] =
if (MIPSInst_RT(ir))
regs->regs[MIPSInst_RT(ir)] =
rt = MIPSInst_RT(inst);
DITOREG(dval, MIPSInst_RT(ir));
DIFROMREG(dval, MIPSInst_RT(ir));
SITOREG(wval, MIPSInst_RT(ir));
SIFROMREG(wval, MIPSInst_RT(ir));
if (MIPSInst_RT(ir) != 0) {
DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
if (MIPSInst_RT(ir) != 0) {
SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
if (MIPSInst_RT(ir) != 0) {
SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
switch (MIPSInst_RT(ir) & 3) {
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
if (MIPSInst_RT(ir))
xcp->regs[MIPSInst_RT(ir)] = value;
if (MIPSInst_RT(ir) == 0)
value = xcp->regs[MIPSInst_RT(ir)];
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);