MIPSInst_RD
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] =
if (((csr & cond) == 0) && MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
if (((csr & cond) != 0) && MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)];
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->hi;
if (MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = regs->lo;
if (!MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = (s64)rs;
if (!MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = res;
if (!MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = res;
if (!MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = res;
if (!MIPSInst_RD(ir))
regs->regs[MIPSInst_RD(ir)] = res;
MIPSInst_RD(ir));
DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
MIPSInst_RD(ir));
SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
MIPSInst_RD(ir));
SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
xcp->regs[MIPSInst_RD(ir)] =
switch (MIPSInst_RD(ir)) {
switch (MIPSInst_RD(ir)) {