MHI_PM_M0
mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2;
#define MHI_REG_ACCESS_VALID(pm_state) ((pm_state & (MHI_PM_POR | MHI_PM_M0 | \
#define MHI_WAKE_DB_CLEAR_VALID(pm_state) (pm_state & (MHI_PM_M0 | \
mhi_cntrl->pm_state == MHI_PM_M0 ||
cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
if (unlikely(cur_state != MHI_PM_M0)) {
MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
MHI_PM_M0,
MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |