Symbol: MIN_POST_DIVR_FREQ
drivers/clk/analogbits/wrpll-cln28hpc.c
193
if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
drivers/clk/analogbits/wrpll-cln28hpc.c
197
max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
drivers/clk/analogbits/wrpll-cln28hpc.c
86
if (post_divr_freq < MIN_POST_DIVR_FREQ ||