MII_READ
data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
if (value != MII_READ) {
} else if (value != MII_READ) {
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
PHY_REALTEK_INIT_REG6, MII_READ);
PHY_REALTEK_INIT_REG2, MII_READ);
phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
PHY_VITESSE_INIT_REG4, MII_READ);
PHY_VITESSE_INIT_REG3, MII_READ);
PHY_VITESSE_INIT_REG4, MII_READ);
PHY_VITESSE_INIT_REG3, MII_READ);
PHY_VITESSE_INIT_REG4, MII_READ);
PHY_VITESSE_INIT_REG3, MII_READ);
reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
MII_CTRL1000, MII_READ);
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
addr = mii_access(phy_id, idx, MII_READ);