MES_PIPE_INST
if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) {
adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) &&
int r, inst = MES_PIPE_INST(xcc_id, pipe);
int inst = MES_PIPE_INST(xcc_id, pipe);
int r, inst = MES_PIPE_INST(xcc_id, pipe);
int r, inst = MES_PIPE_INST(xcc_id, pipe);
int r, inst = MES_PIPE_INST(xcc_id, pipe);
int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)];
int inst = MES_PIPE_INST(xcc_id, pipe);
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
int inst = MES_PIPE_INST(xcc_id, pipe);
struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)];
spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)];
inst = MES_PIPE_INST(xcc_id, pipe);
adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false;
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE);
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready)
adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true;
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe);
mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE;
int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE);
int r, inst = MES_PIPE_INST(xcc_id, pipe);