MIE
#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
or(scc,R9,MIE); /* master interrupt enable */
up->curregs[R9] = NV | MIE;
uap->curregs[R9] |= NV | MIE;
up->curregs[R9] |= MIE;
up->curregs[R9] |= MIE;
up->curregs[R9] |= MIE;
up->curregs[R9] &= ~MIE;
MIE | DLC | NV, /* write 9 */