MEM
MODE_STATUS(MEM),
if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag &
MEM->init.hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
#define RIEBL_MAGIC_ADDR ((unsigned long *)(((char *)MEM) + 0xee8a))
#define RIEBL_HWADDR_ADDR ((unsigned char *)(((char *)MEM) + 0xee8e))
#define RIEBL_IVEC_ADDR ((unsigned short *)(((char *)MEM) + 0xfffe))
#define PKTBUF_ADDR(head) (((unsigned char *)(MEM)) + (head)->base)
MEM = (struct lance_memory *)memaddr;
((((unsigned short *)MEM)[i*2] & 0x0f) << 4) |
((((unsigned short *)MEM)[i*2+1] & 0x0f));
MEM->init.mode = 0x0000; /* Disable Rx and Tx. */
MEM->init.hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
MEM->init.filter[0] = 0x00000000;
MEM->init.filter[1] = 0x00000000;
MEM->init.rx_ring.adr_lo = offsetof( struct lance_memory, rx_head );
MEM->init.rx_ring.adr_hi = 0;
MEM->init.rx_ring.len = RX_RING_LEN_BITS;
MEM->init.tx_ring.adr_lo = offsetof( struct lance_memory, tx_head );
MEM->init.tx_ring.adr_hi = 0;
MEM->init.tx_ring.len = TX_RING_LEN_BITS;
MEM->tx_head[i].base = offset;
MEM->tx_head[i].flag = TMD1_OWN_HOST;
MEM->tx_head[i].base_hi = 0;
MEM->tx_head[i].length = 0;
MEM->tx_head[i].misc = 0;
MEM->rx_head[i].base = offset;
MEM->rx_head[i].flag = TMD1_OWN_CHIP;
MEM->rx_head[i].base_hi = 0;
MEM->rx_head[i].buf_length = -PKT_BUF_SZ;
MEM->rx_head[i].msg_length = 0;
i, MEM->rx_head[i].base,
-MEM->rx_head[i].buf_length,
MEM->rx_head[i].msg_length ));
i, MEM->tx_head[i].base,
-MEM->tx_head[i].length,
MEM->tx_head[i].misc ));
head = &(MEM->tx_head[entry]);
if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
int status = MEM->tx_head[entry].flag;
MEM->tx_head[entry].flag = 0;
int err_status = MEM->tx_head[entry].misc;
MEM->rx_head[entry].flag ));
while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
struct lance_rx_head *head = &(MEM->rx_head[entry]);
#define PKTBUF_ADDR(head) (void *)((unsigned long)(MEM) | (head)->base)
MEM = dvma_malloc_align(sizeof(struct lance_memory), 0x10000);
if (!MEM) {
dvma_free((void *)MEM);
(unsigned long)MEM,
MEM->init.hwaddr[0] = dev->dev_addr[1];
MEM->init.hwaddr[1] = dev->dev_addr[0];
MEM->init.hwaddr[2] = dev->dev_addr[3];
MEM->init.hwaddr[3] = dev->dev_addr[2];
MEM->init.hwaddr[4] = dev->dev_addr[5];
MEM->init.hwaddr[5] = dev->dev_addr[4];
MEM->init.mode = 0x0000;
MEM->init.filter[0] = 0x00000000;
MEM->init.filter[1] = 0x00000000;
MEM->init.rdra = dvma_vtob(MEM->rx_head);
MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
(dvma_vtob(MEM->rx_head) >> 16);
MEM->init.tdra = dvma_vtob(MEM->tx_head);
MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
(dvma_vtob(MEM->tx_head) >> 16);
dvma_vtob(&(MEM->init)), dvma_vtob(MEM->rx_head),
(dvma_vtob(MEM->tx_head))));
MEM->tx_head[i].base = dvma_vtob(MEM->tx_data[i]);
MEM->tx_head[i].flag = 0;
MEM->tx_head[i].base_hi =
(dvma_vtob(MEM->tx_data[i])) >>16;
MEM->tx_head[i].length = 0;
MEM->tx_head[i].misc = 0;
MEM->rx_head[i].base = dvma_vtob(MEM->rx_data[i]);
MEM->rx_head[i].flag = RMD1_OWN_CHIP;
MEM->rx_head[i].base_hi =
(dvma_vtob(MEM->rx_data[i])) >> 16;
MEM->rx_head[i].buf_length = -PKT_BUF_SZ | 0xf000;
MEM->rx_head[i].msg_length = 0;
MEM->init.hwaddr[0] = dev->dev_addr[1];
MEM->init.hwaddr[1] = dev->dev_addr[0];
MEM->init.hwaddr[2] = dev->dev_addr[3];
MEM->init.hwaddr[3] = dev->dev_addr[2];
MEM->init.hwaddr[4] = dev->dev_addr[5];
MEM->init.hwaddr[5] = dev->dev_addr[4];
MEM->init.mode = 0x0000;
MEM->init.filter[0] = 0x00000000;
MEM->init.filter[1] = 0x00000000;
MEM->init.rdra = dvma_vtob(MEM->rx_head);
MEM->init.rlen = (RX_LOG_RING_SIZE << 13) |
(dvma_vtob(MEM->rx_head) >> 16);
MEM->init.tdra = dvma_vtob(MEM->tx_head);
MEM->init.tlen = (TX_LOG_RING_SIZE << 13) |
(dvma_vtob(MEM->tx_head) >> 16);
REGA(CSR1) = dvma_vtob(&(MEM->init));
REGA(CSR2) = dvma_vtob(&(MEM->init)) >> 16;
i, MEM->rx_head[i].base,
-MEM->rx_head[i].buf_length,
MEM->rx_head[i].msg_length);
i, MEM->tx_head[i].base,
-MEM->tx_head[i].length,
MEM->tx_head[i].misc );
head = &(MEM->tx_head[entry]);
if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
struct lance_tx_head *head = &(MEM->tx_head[old_tx]);
while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
struct lance_rx_head *head = &(MEM->rx_head[entry]);
if (ibmphp_find_resource(bus, start_address, &mem, MEM) < 0) {
if (ibmphp_find_resource(bus, start_address, &mem, MEM) < 0) {
mem_tmp->type = MEM;
mem[count]->type = MEM;
mem_tmp->type = MEM;
bus_mem[count]->type = MEM;
mem->type = MEM;
mem_tmp->type = MEM;
case MEM:
case MEM:
case MEM:
if (ibmphp_find_resource(bus_prev, range_cur->start, &res, MEM) < 0)
case MEM:
mem->type = MEM;
case MEM:
if (!range_exists_already(range, bus_sec, MEM)) {
add_bus_range(MEM, range, bus_sec);
if (ibmphp_find_resource(bus_cur, start_address, &mem, MEM)) {
mem->type = MEM;
rc = alloc_bus_range(&newbus, &newrange, curr, MEM, 1);
rc = alloc_bus_range(&bus_cur, &newrange, curr, MEM, 0);
rc = alloc_bus_range(&newbus, &newrange, curr, MEM, 1);
new_mem->type = MEM;
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
case MEM:
#define PIPEMEM(x) MEM(x)
INSN_3(STX, MEM, B), \
INSN_3(STX, MEM, H), \
INSN_3(STX, MEM, W), \
INSN_3(STX, MEM, DW), \
INSN_3(ST, MEM, B), \
INSN_3(ST, MEM, H), \
INSN_3(ST, MEM, W), \
INSN_3(ST, MEM, DW), \
INSN_3(LDX, MEM, B), \
INSN_3(LDX, MEM, H), \
INSN_3(LDX, MEM, W), \
INSN_3(LDX, MEM, DW), \
state->mode = MEM;
case MEM:
if (GET_CODE(body) != MEM)