MHICTRL_RESET_MASK
mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHICTRL, MHICTRL_RESET_MASK, 0);
*mhi_reset = !!FIELD_GET(MHICTRL_RESET_MASK, regval);
MHICTRL_RESET_MASK, 0, interval_us,
MHICTRL_RESET_MASK, 1);
MHICTRL_RESET_MASK, 0, interval_us,
MHICTRL_RESET_MASK, 0, 25000, mhi_cntrl->timeout_ms);
MHICTRL_RESET_MASK,
ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);