arch/powerpc/platforms/cell/spu_base.c

699

tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/backing_ops.c

301

sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/backing_ops.c

312

sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/hw_ops.c

231

sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/hw_ops.c

242

sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;

arch/powerpc/platforms/cell/spufs/switch.c

1043

MFC_STATE1_MASTER_RUN_CONTROL_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1055

MFC_STATE1_MASTER_RUN_CONTROL_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

1882

spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);

arch/powerpc/platforms/cell/spufs/switch.c

2148

MFC_STATE1_MASTER_RUN_CONTROL_MASK |

arch/powerpc/platforms/cell/spufs/switch.c

496

spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |