MFC_STATE1_MASTER_RUN_CONTROL_MASK
tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
MFC_STATE1_MASTER_RUN_CONTROL_MASK);
MFC_STATE1_MASTER_RUN_CONTROL_MASK);
spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
MFC_STATE1_MASTER_RUN_CONTROL_MASK |
spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |