Symbol: MDIO_MMD_VEND1
drivers/net/dsa/mv88e6xxx/pcs-639x.c
680
{ MDIO_MMD_VEND1, 0x8093, 0xcb5a, 0xffff },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
681
{ MDIO_MMD_VEND1, 0x8171, 0x7088, 0xffff },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
682
{ MDIO_MMD_VEND1, 0x80c9, 0x311a, 0xffff },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
683
{ MDIO_MMD_VEND1, 0x80a2, 0x8000, 0xff7f },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
684
{ MDIO_MMD_VEND1, 0x80a9, 0x0000, 0xfff0 },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
685
{ MDIO_MMD_VEND1, 0x80a3, 0x0000, 0xf8ff },
drivers/net/dsa/mv88e6xxx/pcs-639x.c
736
return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_VEND1, 0x8000, 0x58);
drivers/net/dsa/mxl862xx/mxl862xx-host.c
193
return __mdiodev_c45_read(priv->mdiodev, MDIO_MMD_VEND1, addr);
drivers/net/dsa/mxl862xx/mxl862xx-host.c
198
return __mdiodev_c45_write(priv->mdiodev, MDIO_MMD_VEND1, addr, data);
drivers/net/dsa/sja1105/sja1105_mdio.c
20
if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
drivers/net/dsa/sja1105/sja1105_mdio.c
46
if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
drivers/net/ethernet/aquantia/atlantic/aq_phy.c
165
val = aq_phy_read_reg(aq_hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/aq_phy.c
168
aq_phy_write_reg(aq_hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
108
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
111
aq_mss_mdio_write(hw, MDIO_MMD_VEND1, MSS_INGRESS_LUT_CTL_REGISTER_ADDR,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
137
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
142
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
151
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
157
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
180
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
183
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
190
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
192
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2001
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1, MSS_EGRESS_CTL_REGISTER_ADDR,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2005
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2013
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2017
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2024
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2028
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2035
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2039
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
204
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
207
aq_mss_mdio_write(hw, MDIO_MMD_VEND1, MSS_EGRESS_LUT_CTL_REGISTER_ADDR,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
230
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2317
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2321
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2329
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2333
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2340
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2344
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
235
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2351
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2355
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2374
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2382
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2406
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2413
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2435
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
244
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2441
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2459
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
2465
ret = aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
250
ret = aq_mss_mdio_read(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
83
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
86
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
94
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/aquantia/atlantic/macsec/macsec_api.c
97
aq_mss_mdio_write(hw, MDIO_MMD_VEND1,
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
110
err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
292
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
319
t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
328
err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
332
err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
71
int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
86
err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
92
return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0);
drivers/net/ethernet/chelsio/cxgb3/aq100x.c
99
t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v);
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
1303
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
2844
status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, &reg);
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
2856
status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2341
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2349
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2358
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2374
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2455
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2464
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2471
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2480
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2487
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2495
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2728
MDIO_MMD_VEND1, &phy_data);
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2731
MDIO_MMD_VEND1, phy_data);
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2750
MDIO_MMD_VEND1, &phy_data);
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
2753
MDIO_MMD_VEND1, phy_data);
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
3340
MDIO_MMD_VEND1,
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
3349
MDIO_MMD_VEND1,
drivers/net/ethernet/microchip/lan743x_ethtool.c
1237
{ ETH_SR_VSMMD_DEV_ID1, MDIO_MMD_VEND1, 0x0002},
drivers/net/ethernet/microchip/lan743x_ethtool.c
1238
{ ETH_SR_VSMMD_DEV_ID2, MDIO_MMD_VEND1, 0x0003},
drivers/net/ethernet/microchip/lan743x_ethtool.c
1239
{ ETH_SR_VSMMD_PCS_ID1, MDIO_MMD_VEND1, 0x0004},
drivers/net/ethernet/microchip/lan743x_ethtool.c
1240
{ ETH_SR_VSMMD_PCS_ID2, MDIO_MMD_VEND1, 0x0005},
drivers/net/ethernet/microchip/lan743x_ethtool.c
1241
{ ETH_SR_VSMMD_STS, MDIO_MMD_VEND1, 0x0008},
drivers/net/ethernet/microchip/lan743x_ethtool.c
1242
{ ETH_SR_VSMMD_CTRL, MDIO_MMD_VEND1, 0x0009},
drivers/net/phy/adin.c
281
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
285
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
drivers/net/phy/adin.c
317
return phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
327
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
331
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
drivers/net/phy/adin.c
344
return phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
444
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
drivers/net/phy/adin.c
459
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
464
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
524
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
drivers/net/phy/adin.c
536
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
632
if (devad == MDIO_MMD_VEND1)
drivers/net/phy/adin.c
800
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
809
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
834
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
drivers/net/phy/adin.c
843
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
drivers/net/phy/adin.c
919
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
drivers/net/phy/adin.c
951
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
962
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin.c
998
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
drivers/net/phy/adin1100.c
196
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/adin1100.c
202
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
drivers/net/phy/adin1100.c
235
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
drivers/net/phy/adin1100.c
239
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
drivers/net/phy/air_an8801.c
958
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/air_an8801.c
965
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
drivers/net/phy/air_an8801.c
971
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
drivers/net/phy/air_an8801.c
976
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
drivers/net/phy/air_en8811h.c
1299
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
drivers/net/phy/air_en8811h.c
1303
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
drivers/net/phy/air_en8811h.c
1307
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
drivers/net/phy/air_en8811h.c
1311
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
drivers/net/phy/air_en8811h.c
1456
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
drivers/net/phy/air_en8811h.c
1461
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
drivers/net/phy/air_en8811h.c
337
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_firmware.c
102
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_firmware.c
116
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
drivers/net/phy/aquantia/aquantia_firmware.c
118
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
drivers/net/phy/aquantia/aquantia_firmware.c
121
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
drivers/net/phy/aquantia/aquantia_firmware.c
138
up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
drivers/net/phy/aquantia/aquantia_firmware.c
262
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
drivers/net/phy/aquantia/aquantia_firmware.c
280
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
drivers/net/phy/aquantia/aquantia_firmware.c
284
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
drivers/net/phy/aquantia/aquantia_firmware.c
290
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
drivers/net/phy/aquantia/aquantia_firmware.c
96
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_firmware.c
99
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_hwmon.c
44
int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
drivers/net/phy/aquantia/aquantia_hwmon.c
65
return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
drivers/net/phy/aquantia/aquantia_hwmon.c
70
int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
drivers/net/phy/aquantia/aquantia_leds.c
113
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
drivers/net/phy/aquantia/aquantia_leds.c
122
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
drivers/net/phy/aquantia/aquantia_leds.c
17
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
drivers/net/phy/aquantia/aquantia_leds.c
55
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index));
drivers/net/phy/aquantia/aquantia_main.c
1006
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
drivers/net/phy/aquantia/aquantia_main.c
1026
err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_main.c
1052
err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
drivers/net/phy/aquantia/aquantia_main.c
1064
err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
drivers/net/phy/aquantia/aquantia_main.c
1154
err = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_main.c
270
err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
drivers/net/phy/aquantia/aquantia_main.c
275
err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
drivers/net/phy/aquantia/aquantia_main.c
697
false, phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_main.c
715
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
drivers/net/phy/aquantia/aquantia_main.c
722
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
drivers/net/phy/aquantia/aquantia_main.c
845
val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/aquantia/aquantia_main.c
924
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
303
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,
drivers/net/phy/as21xxx.c
308
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_FW_START_ADDR,
drivers/net/phy/as21xxx.c
313
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
319
val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
330
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
336
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
342
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
348
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLB_REG_CPU_CTRL,
drivers/net/phy/as21xxx.c
400
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS, val,
drivers/net/phy/as21xxx.c
423
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_CMD, cmd);
drivers/net/phy/as21xxx.c
440
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_STS);
drivers/net/phy/as21xxx.c
472
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i),
drivers/net/phy/as21xxx.c
507
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_IPC_DATA(i));
drivers/net/phy/as21xxx.c
628
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK,
drivers/net/phy/as21xxx.c
730
speed = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
782
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
811
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_LED_REG(index));
drivers/net/phy/as21xxx.c
841
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/as21xxx.c
874
return phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/bcm84881.c
381
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 0x4011);
drivers/net/phy/mediatek/mtk-2p5ge.c
124
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
drivers/net/phy/mediatek/mtk-2p5ge.c
88
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100);
drivers/net/phy/mediatek/mtk-2p5ge.c
89
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df);
drivers/net/phy/mediatek/mtk-ge-soc.c
1000
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
drivers/net/phy/mediatek/mtk-ge-soc.c
1005
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
drivers/net/phy/mediatek/mtk-ge-soc.c
1012
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
drivers/net/phy/mediatek/mtk-ge-soc.c
1016
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
drivers/net/phy/mediatek/mtk-ge-soc.c
1021
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
drivers/net/phy/mediatek/mtk-ge-soc.c
1070
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
1399
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
drivers/net/phy/mediatek/mtk-ge-soc.c
394
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
drivers/net/phy/mediatek/mtk-ge-soc.c
397
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
407
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
drivers/net/phy/mediatek/mtk-ge-soc.c
409
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
drivers/net/phy/mediatek/mtk-ge-soc.c
420
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
drivers/net/phy/mediatek/mtk-ge-soc.c
441
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
drivers/net/phy/mediatek/mtk-ge-soc.c
443
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
drivers/net/phy/mediatek/mtk-ge-soc.c
445
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
drivers/net/phy/mediatek/mtk-ge-soc.c
447
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
drivers/net/phy/mediatek/mtk-ge-soc.c
501
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
drivers/net/phy/mediatek/mtk-ge-soc.c
505
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
drivers/net/phy/mediatek/mtk-ge-soc.c
509
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
drivers/net/phy/mediatek/mtk-ge-soc.c
513
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
drivers/net/phy/mediatek/mtk-ge-soc.c
518
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
drivers/net/phy/mediatek/mtk-ge-soc.c
522
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
drivers/net/phy/mediatek/mtk-ge-soc.c
526
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
drivers/net/phy/mediatek/mtk-ge-soc.c
530
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
drivers/net/phy/mediatek/mtk-ge-soc.c
535
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
drivers/net/phy/mediatek/mtk-ge-soc.c
539
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
drivers/net/phy/mediatek/mtk-ge-soc.c
543
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
drivers/net/phy/mediatek/mtk-ge-soc.c
547
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
drivers/net/phy/mediatek/mtk-ge-soc.c
552
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
drivers/net/phy/mediatek/mtk-ge-soc.c
556
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
drivers/net/phy/mediatek/mtk-ge-soc.c
560
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
drivers/net/phy/mediatek/mtk-ge-soc.c
564
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
drivers/net/phy/mediatek/mtk-ge-soc.c
613
phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
drivers/net/phy/mediatek/mtk-ge-soc.c
650
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
drivers/net/phy/mediatek/mtk-ge-soc.c
652
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
drivers/net/phy/mediatek/mtk-ge-soc.c
654
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
drivers/net/phy/mediatek/mtk-ge-soc.c
659
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
662
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
665
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
670
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
673
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
676
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
681
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
684
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
687
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
692
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
695
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
698
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
713
ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
drivers/net/phy/mediatek/mtk-ge-soc.c
732
lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
742
upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
763
cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
drivers/net/phy/mediatek/mtk-ge-soc.c
774
cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
drivers/net/phy/mediatek/mtk-ge-soc.c
794
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
drivers/net/phy/mediatek/mtk-ge-soc.c
796
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
drivers/net/phy/mediatek/mtk-ge-soc.c
798
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
drivers/net/phy/mediatek/mtk-ge-soc.c
800
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
drivers/net/phy/mediatek/mtk-ge-soc.c
858
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
drivers/net/phy/mediatek/mtk-ge-soc.c
888
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
drivers/net/phy/mediatek/mtk-ge-soc.c
894
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
drivers/net/phy/mediatek/mtk-ge-soc.c
897
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
drivers/net/phy/mediatek/mtk-ge-soc.c
898
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
drivers/net/phy/mediatek/mtk-ge-soc.c
899
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
drivers/net/phy/mediatek/mtk-ge-soc.c
900
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
drivers/net/phy/mediatek/mtk-ge-soc.c
901
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
drivers/net/phy/mediatek/mtk-ge-soc.c
902
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
drivers/net/phy/mediatek/mtk-ge-soc.c
903
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
drivers/net/phy/mediatek/mtk-ge-soc.c
904
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
drivers/net/phy/mediatek/mtk-ge-soc.c
905
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
drivers/net/phy/mediatek/mtk-ge-soc.c
906
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
drivers/net/phy/mediatek/mtk-ge-soc.c
909
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
drivers/net/phy/mediatek/mtk-ge-soc.c
911
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
drivers/net/phy/mediatek/mtk-ge-soc.c
915
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
drivers/net/phy/mediatek/mtk-ge-soc.c
916
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
drivers/net/phy/mediatek/mtk-ge-soc.c
918
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
drivers/net/phy/mediatek/mtk-ge-soc.c
930
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
drivers/net/phy/mediatek/mtk-ge-soc.c
933
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
drivers/net/phy/mediatek/mtk-ge-soc.c
956
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
drivers/net/phy/mediatek/mtk-ge-soc.c
962
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
drivers/net/phy/mediatek/mtk-ge-soc.c
967
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
974
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
980
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
984
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
987
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge-soc.c
990
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
drivers/net/phy/mediatek/mtk-ge-soc.c
996
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
drivers/net/phy/mediatek/mtk-ge.c
49
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge.c
59
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mediatek/mtk-ge.c
82
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
drivers/net/phy/mediatek/mtk-ge.c
87
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
drivers/net/phy/mediatek/mtk-ge.c
91
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
drivers/net/phy/microchip_t1.c
1094
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1101
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
drivers/net/phy/microchip_t1.c
1108
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1118
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1128
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1135
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
drivers/net/phy/microchip_t1.c
1144
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
drivers/net/phy/microchip_t1.c
1150
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
drivers/net/phy/microchip_t1.c
1165
txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
drivers/net/phy/microchip_t1.c
1170
rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
drivers/net/phy/microchip_t1.c
1206
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
drivers/net/phy/microchip_t1.c
1212
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
drivers/net/phy/microchip_t1.c
1223
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
drivers/net/phy/microchip_t1.c
1286
priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1293
phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1305
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1314
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1351
{MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
drivers/net/phy/microchip_t1.c
1352
{MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
drivers/net/phy/microchip_t1.c
1353
{MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
drivers/net/phy/microchip_t1.c
1354
{MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
drivers/net/phy/microchip_t1.c
1355
{MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
drivers/net/phy/microchip_t1.c
1356
{MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
drivers/net/phy/microchip_t1.c
1358
{MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
drivers/net/phy/microchip_t1.c
1359
{MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
drivers/net/phy/microchip_t1.c
1360
{MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
drivers/net/phy/microchip_t1.c
1361
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
drivers/net/phy/microchip_t1.c
1362
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
drivers/net/phy/microchip_t1.c
1363
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
drivers/net/phy/microchip_t1.c
1364
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
drivers/net/phy/microchip_t1.c
1365
{MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
drivers/net/phy/microchip_t1.c
1366
{MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
drivers/net/phy/microchip_t1.c
1385
{MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
drivers/net/phy/microchip_t1.c
1392
{MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
drivers/net/phy/microchip_t1.c
1400
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
drivers/net/phy/microchip_t1.c
1447
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
drivers/net/phy/microchip_t1.c
1453
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
drivers/net/phy/microchip_t1.c
1557
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
drivers/net/phy/microchip_t1.c
1562
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
drivers/net/phy/microchip_t1.c
1565
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
drivers/net/phy/microchip_t1.c
1570
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
drivers/net/phy/microchip_t1.c
1592
irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
drivers/net/phy/microchip_t1.c
1616
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,
drivers/net/phy/microchip_t1.c
1655
{MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
drivers/net/phy/microchip_t1.c
1656
{MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
drivers/net/phy/microchip_t1.c
1657
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
drivers/net/phy/microchip_t1.c
1658
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
drivers/net/phy/microchip_t1.c
1659
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
drivers/net/phy/microchip_t1.c
1660
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
drivers/net/phy/microchip_t1.c
1661
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
drivers/net/phy/microchip_t1.c
1662
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
drivers/net/phy/microchip_t1.c
1663
{MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
drivers/net/phy/microchip_t1.c
1684
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1714
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
drivers/net/phy/microchip_t1.c
1727
return phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1744
rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1752
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1762
return phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1799
gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1806
pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1813
neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1820
pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1827
neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1880
gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1887
pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1933
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1983
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
1989
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100,
drivers/net/phy/microchip_t1.c
1994
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100);
drivers/net/phy/microchip_t1.c
1998
rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
drivers/net/phy/microchip_t1.c
2019
rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
2025
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
2086
rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
2093
rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/microchip_t1.c
2101
rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS);
drivers/net/phy/microchip_t1.c
314
{ "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
drivers/net/phy/microchip_t1.c
315
{ "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
drivers/net/phy/microchip_t1.c
316
{ "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
drivers/net/phy/microchip_t1.c
317
{ "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
drivers/net/phy/microchip_t1.c
318
{ "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
drivers/net/phy/microchip_t1.c
319
{ "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
drivers/net/phy/mxl-gpy.c
1018
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val);
drivers/net/phy/mxl-gpy.c
1071
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
drivers/net/phy/mxl-gpy.c
199
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
drivers/net/phy/mxl-gpy.c
219
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
drivers/net/phy/mxl-gpy.c
307
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
drivers/net/phy/mxl-gpy.c
315
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
drivers/net/phy/mxl-gpy.c
324
ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/mxl-gpy.c
331
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
drivers/net/phy/mxl-gpy.c
426
phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
drivers/net/phy/mxl-gpy.c
435
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
drivers/net/phy/mxl-gpy.c
553
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
drivers/net/phy/mxl-gpy.c
600
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
drivers/net/phy/mxl-gpy.c
917
return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0);
drivers/net/phy/mxl-gpy.c
951
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index));
drivers/net/phy/nxp-c45-tja11xx-macsec.c
1608
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
drivers/net/phy/nxp-c45-tja11xx.c
1058
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1063
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1102
NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 8, 6), },
drivers/net/phy/nxp-c45-tja11xx.c
1104
NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 0, 6), },
drivers/net/phy/nxp-c45-tja11xx.c
1106
NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 10, 6), },
drivers/net/phy/nxp-c45-tja11xx.c
1108
NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 0, 10), },
drivers/net/phy/nxp-c45-tja11xx.c
1110
NXP_C45_REG_FIELD(0x8350, MDIO_MMD_VEND1, 0, 16) },
drivers/net/phy/nxp-c45-tja11xx.c
1115
NXP_C45_REG_FIELD(0xAFCE, MDIO_MMD_VEND1, 0, 6), },
drivers/net/phy/nxp-c45-tja11xx.c
1117
NXP_C45_REG_FIELD(0xAFCF, MDIO_MMD_VEND1, 0, 6), },
drivers/net/phy/nxp-c45-tja11xx.c
1119
NXP_C45_REG_FIELD(0xAFD0, MDIO_MMD_VEND1, 0, 9), },
drivers/net/phy/nxp-c45-tja11xx.c
1121
NXP_C45_REG_FIELD(0xAFD1, MDIO_MMD_VEND1, 0, 9), },
drivers/net/phy/nxp-c45-tja11xx.c
1126
NXP_C45_REG_FIELD(0x8351, MDIO_MMD_VEND1, 0, 14) },
drivers/net/phy/nxp-c45-tja11xx.c
1128
NXP_C45_REG_FIELD(0xACA1, MDIO_MMD_VEND1, 0, 8), },
drivers/net/phy/nxp-c45-tja11xx.c
1130
NXP_C45_REG_FIELD(0xACA0, MDIO_MMD_VEND1, 0, 16), },
drivers/net/phy/nxp-c45-tja11xx.c
1132
NXP_C45_REG_FIELD(0xACA3, MDIO_MMD_VEND1, 0, 8), },
drivers/net/phy/nxp-c45-tja11xx.c
1134
NXP_C45_REG_FIELD(0xACA2, MDIO_MMD_VEND1, 0, 16), },
drivers/net/phy/nxp-c45-tja11xx.c
1136
NXP_C45_REG_FIELD(0xACA5, MDIO_MMD_VEND1, 0, 8), },
drivers/net/phy/nxp-c45-tja11xx.c
1138
NXP_C45_REG_FIELD(0xACA4, MDIO_MMD_VEND1, 0, 16), },
drivers/net/phy/nxp-c45-tja11xx.c
1140
NXP_C45_REG_FIELD(0xACA7, MDIO_MMD_VEND1, 0, 8), },
drivers/net/phy/nxp-c45-tja11xx.c
1142
NXP_C45_REG_FIELD(0xACA6, MDIO_MMD_VEND1, 0, 16), },
drivers/net/phy/nxp-c45-tja11xx.c
1197
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1202
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1204
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1206
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1214
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1223
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1228
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1232
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1237
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1246
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE,
drivers/net/phy/nxp-c45-tja11xx.c
1259
ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1263
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1280
irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS);
drivers/net/phy/nxp-c45-tja11xx.c
1282
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK,
drivers/net/phy/nxp-c45-tja11xx.c
1295
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1313
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL,
drivers/net/phy/nxp-c45-tja11xx.c
1320
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1330
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1332
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
drivers/net/phy/nxp-c45-tja11xx.c
1371
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
drivers/net/phy/nxp-c45-tja11xx.c
1373
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1383
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY);
drivers/net/phy/nxp-c45-tja11xx.c
1398
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1400
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1429
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER,
drivers/net/phy/nxp-c45-tja11xx.c
1439
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1460
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE);
drivers/net/phy/nxp-c45-tja11xx.c
1461
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE);
drivers/net/phy/nxp-c45-tja11xx.c
1474
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
drivers/net/phy/nxp-c45-tja11xx.c
1477
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID,
drivers/net/phy/nxp-c45-tja11xx.c
1484
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
drivers/net/phy/nxp-c45-tja11xx.c
1487
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID,
drivers/net/phy/nxp-c45-tja11xx.c
1538
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
drivers/net/phy/nxp-c45-tja11xx.c
1547
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1558
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1571
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1579
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1594
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1602
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1622
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_ID3);
drivers/net/phy/nxp-c45-tja11xx.c
1632
phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1642
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x4b95);
drivers/net/phy/nxp-c45-tja11xx.c
1643
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0xf3cd);
drivers/net/phy/nxp-c45-tja11xx.c
1645
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x89c7);
drivers/net/phy/nxp-c45-tja11xx.c
1646
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0893);
drivers/net/phy/nxp-c45-tja11xx.c
1649
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x0476, 0x58a0);
drivers/net/phy/nxp-c45-tja11xx.c
1654
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 0x0);
drivers/net/phy/nxp-c45-tja11xx.c
1655
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 0x0);
drivers/net/phy/nxp-c45-tja11xx.c
1661
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1664
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1684
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1);
drivers/net/phy/nxp-c45-tja11xx.c
1685
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2);
drivers/net/phy/nxp-c45-tja11xx.c
1690
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1753
phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1810
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT,
drivers/net/phy/nxp-c45-tja11xx.c
1812
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT,
drivers/net/phy/nxp-c45-tja11xx.c
1814
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH,
drivers/net/phy/nxp-c45-tja11xx.c
1816
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH,
drivers/net/phy/nxp-c45-tja11xx.c
1822
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL,
drivers/net/phy/nxp-c45-tja11xx.c
1824
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES,
drivers/net/phy/nxp-c45-tja11xx.c
1831
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1835
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1845
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1848
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1859
NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 3, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1861
NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 2, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1863
NXP_C45_REG_FIELD(0x1115, MDIO_MMD_VEND1, 0, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1865
NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 2, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1867
NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 0, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1879
NXP_C45_REG_FIELD(0x1131, MDIO_MMD_VEND1, 0, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1881
NXP_C45_REG_FIELD(0x1132, MDIO_MMD_VEND1, 0, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1883
NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 0, 8),
drivers/net/phy/nxp-c45-tja11xx.c
1885
NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 8, 4),
drivers/net/phy/nxp-c45-tja11xx.c
1887
NXP_C45_REG_FIELD(0x114F, MDIO_MMD_VEND1, 0, 16),
drivers/net/phy/nxp-c45-tja11xx.c
1889
NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 14, 2),
drivers/net/phy/nxp-c45-tja11xx.c
1891
NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 12, 3),
drivers/net/phy/nxp-c45-tja11xx.c
1893
NXP_C45_REG_FIELD(0x1150, MDIO_MMD_VEND1, 0, 16),
drivers/net/phy/nxp-c45-tja11xx.c
1895
NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 0, 14),
drivers/net/phy/nxp-c45-tja11xx.c
1903
NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 13, 1),
drivers/net/phy/nxp-c45-tja11xx.c
1905
NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 0, 3),
drivers/net/phy/nxp-c45-tja11xx.c
1925
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD,
drivers/net/phy/nxp-c45-tja11xx.c
1927
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS,
drivers/net/phy/nxp-c45-tja11xx.c
1929
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1935
phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL,
drivers/net/phy/nxp-c45-tja11xx.c
1937
phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE,
drivers/net/phy/nxp-c45-tja11xx.c
1939
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG,
drivers/net/phy/nxp-c45-tja11xx.c
1946
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1950
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1960
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1963
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
1975
phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
2009
NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 4, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2011
NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 5, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2013
NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 2, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2015
NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 1, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2017
NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 2, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2029
NXP_C45_REG_FIELD(0x900A, MDIO_MMD_VEND1, 1, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2031
NXP_C45_REG_FIELD(0x900C, MDIO_MMD_VEND1, 1, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2033
NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 8, 8),
drivers/net/phy/nxp-c45-tja11xx.c
2035
NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 4, 4),
drivers/net/phy/nxp-c45-tja11xx.c
2037
NXP_C45_REG_FIELD(0x9062, MDIO_MMD_VEND1, 0, 16),
drivers/net/phy/nxp-c45-tja11xx.c
2039
NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 0, 2),
drivers/net/phy/nxp-c45-tja11xx.c
2041
NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 2, 3),
drivers/net/phy/nxp-c45-tja11xx.c
2043
NXP_C45_REG_FIELD(0x9063, MDIO_MMD_VEND1, 0, 16),
drivers/net/phy/nxp-c45-tja11xx.c
2045
NXP_C45_REG_FIELD(0x9064, MDIO_MMD_VEND1, 0, 14),
drivers/net/phy/nxp-c45-tja11xx.c
2053
NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 15, 1),
drivers/net/phy/nxp-c45-tja11xx.c
2055
NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 0, 3),
drivers/net/phy/nxp-c45-tja11xx.c
393
ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
395
ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
397
ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
399
ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
424
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0,
drivers/net/phy/nxp-c45-tja11xx.c
426
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1,
drivers/net/phy/nxp-c45-tja11xx.c
428
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0,
drivers/net/phy/nxp-c45-tja11xx.c
430
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1,
drivers/net/phy/nxp-c45-tja11xx.c
464
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
472
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
519
extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
521
extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
523
extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
525
extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
527
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
538
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
554
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
566
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
605
phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL,
drivers/net/phy/nxp-c45-tja11xx.c
607
reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0);
drivers/net/phy/nxp-c45-tja11xx.c
623
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S);
drivers/net/phy/nxp-c45-tja11xx.c
638
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END);
drivers/net/phy/nxp-c45-tja11xx.c
648
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
655
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S,
drivers/net/phy/nxp-c45-tja11xx.c
754
phy_write_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
820
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
824
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
836
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
840
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
845
phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/nxp-c45-tja11xx.c
849
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/phy_device.c
918
if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
drivers/net/phy/phy_device.c
960
if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) {
drivers/net/phy/realtek/realtek_main.c
1507
return phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8226_VND1_UNKNOWN_6A21,
drivers/net/phy/realtek/realtek_main.c
1678
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
drivers/net/phy/realtek/realtek_main.c
1683
ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
drivers/net/phy/realtek/realtek_main.c
1690
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
drivers/net/phy/realtek/realtek_main.c
1694
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
drivers/net/phy/realtek/realtek_main.c
1698
return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
drivers/net/phy/realtek/realtek_main.c
1715
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_ADDR, reg);
drivers/net/phy/realtek/realtek_main.c
1719
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_DATA, val);
drivers/net/phy/realtek/realtek_main.c
1723
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CMD,
drivers/net/phy/realtek/realtek_main.c
1729
return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
drivers/net/phy/realtek/realtek_main.c
1765
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
drivers/net/phy/realtek/realtek_main.c
1822
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
drivers/net/phy/realtek/realtek_main.c
2320
return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/realtek/realtek_main.c
2345
return rtl8224_package_modify_mmd(phydev, MDIO_MMD_VEND1,
drivers/net/phy/teranetics.c
39
if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93))
drivers/net/phy/teranetics.c
54
if (!phy_read_mmd(phydev, MDIO_MMD_VEND1, 93)) {
include/uapi/linux/mdio.h
189
#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)