MCR_REG
#define BDW_SCRATCH1 MCR_REG(0xb11c)
#define GEN11_SCRATCH2 MCR_REG(0xb140)
#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
#define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8)
#define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc)
#define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0)
#define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4)
#define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04)
#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
#define COMP_MOD_CTRL MCR_REG(0xcf30)
#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
#define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
#define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
#define GEN8_ROW_INSTDONE MCR_REG(0xe164)
#define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
#define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
#define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c)
#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
#define RT_CTRL MCR_REG(0xe530)
#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define ICL_HDC_MODE MCR_REG(0xe5f4)
#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
#define SARB_CHICKEN1 MCR_REG(0xe90c)
#define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index))
#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
#define GEN8_WM_CHICKEN2 MCR_REG(0x5584)
#define XEHP_CULLBIT1 MCR_REG(0x6100)
#define CHICKEN_RASTER_2 MCR_REG(0x6208)
#define VFLSKPD MCR_REG(0x62a8)
#define XEHP_FF_MODE2 MCR_REG(0x6604)
#define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
#define XEHP_CULLBIT2 MCR_REG(0x7030)
#define XEHP_PSS_MODE2 MCR_REG(0x703c)
#define XEHP_PSS_CHICKEN MCR_REG(0x7044)
#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
#define XEHP_SQCM MCR_REG(0x8724)
#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
#define SSMCGCTL9530 MCR_REG(0x9530)
#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4)
#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
#define GEN8_L3SQCREG1 MCR_REG(0xb100)
#define GEN8_L3SQCREG4 MCR_REG(0xb118)
#define GEN9_SCRATCH1 MCR_REG(0xb11c)
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);
ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);