Symbol: MC_VM_MX_L1_TLB_CNTL
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
356
u64 MC_VM_MX_L1_TLB_CNTL;
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
161
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
162
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
163
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
165
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
167
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
169
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
358
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
360
MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
206
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
208
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
210
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
212
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
214
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
216
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
461
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
463
MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
581
adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
618
WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
627
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
628
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
629
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
630
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
631
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
747
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
748
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
749
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
844
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
845
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
846
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
847
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
848
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
981
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
982
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
983
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
144
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
145
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
146
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
148
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
150
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
152
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
403
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
405
MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
162
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
163
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
164
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
166
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
168
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
170
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
387
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
389
MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
201
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
203
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
205
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
207
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
209
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
211
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
219
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
221
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
223
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
225
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
227
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
229
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
487
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
488
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
495
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
497
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/radeon/cik.c
5431
WREG32(MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/radeon/cik.c
5553
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
drivers/gpu/drm/radeon/ni.c
1260
WREG32(MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/radeon/ni.c
1345
WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
drivers/gpu/drm/radeon/si.c
4277
WREG32(MC_VM_MX_L1_TLB_CNTL,
drivers/gpu/drm/radeon/si.c
4370
WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |