MC_SEQ_WR_CTL_D1
case MC_SEQ_WR_CTL_D1:
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
case MC_SEQ_WR_CTL_D1 >> 2:
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
case MC_SEQ_WR_CTL_D1 >> 2:
case MC_SEQ_WR_CTL_D1:
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
case MC_SEQ_WR_CTL_D1 >> 2:
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
case MC_SEQ_WR_CTL_D1 >> 2:
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));