MC_SEQ_RD_CTL_D0
case MC_SEQ_RD_CTL_D0:
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
case MC_SEQ_RD_CTL_D0 >> 2:
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
case MC_SEQ_RD_CTL_D0 >> 2:
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
case MC_SEQ_RD_CTL_D0 >> 2:
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
case MC_SEQ_RD_CTL_D0 >> 2:
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));