MC_SEQ_MISC_TIMING2_LP
*out_reg = MC_SEQ_MISC_TIMING2_LP;
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
*out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));