MC_SEQ_MISC_TIMING2
case MC_SEQ_MISC_TIMING2:
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
case MC_SEQ_MISC_TIMING2 >> 2:
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
case MC_SEQ_MISC_TIMING2 >> 2:
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
case MC_SEQ_MISC_TIMING2 >> 2:
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
case MC_SEQ_MISC_TIMING2 >> 2:
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));