Symbol: MCHBAR_MIRROR_BASE_SNB
drivers/gpu/drm/i915/display/intel_mchbar.c
22
return MCHBAR_MIRROR_BASE_SNB;
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
715
MMIO_F(_MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000);
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
21
#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
30
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
35
#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
37
#define PCU_CR_PACKAGE_TEMPERATURE XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5978)
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
40
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
drivers/gpu/drm/xe/xe_guc_pc.c
42
#define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
drivers/gpu/drm/xe/xe_guc_pc.c
47
#define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
include/drm/intel/mchbar_regs.h
104
#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \
include/drm/intel/mchbar_regs.h
130
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
include/drm/intel/mchbar_regs.h
133
#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
include/drm/intel/mchbar_regs.h
137
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
include/drm/intel/mchbar_regs.h
145
#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
include/drm/intel/mchbar_regs.h
146
#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
include/drm/intel/mchbar_regs.h
147
#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
include/drm/intel/mchbar_regs.h
166
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
include/drm/intel/mchbar_regs.h
167
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
include/drm/intel/mchbar_regs.h
203
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
include/drm/intel/mchbar_regs.h
210
#define PCU_PACKAGE_POWER_SKU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5930)
include/drm/intel/mchbar_regs.h
218
#define PCU_PACKAGE_POWER_SKU_UNIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5938)
include/drm/intel/mchbar_regs.h
222
#define PCU_PACKAGE_ENERGY_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x593c)
include/drm/intel/mchbar_regs.h
224
#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
include/drm/intel/mchbar_regs.h
226
#define PCU_PACKAGE_TEMPERATURE _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5978)
include/drm/intel/mchbar_regs.h
229
#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
include/drm/intel/mchbar_regs.h
230
#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
include/drm/intel/mchbar_regs.h
235
#define GEN10_FREQ_INFO_REC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
include/drm/intel/mchbar_regs.h
237
#define PCU_PACKAGE_RAPL_LIMIT _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
include/drm/intel/mchbar_regs.h
245
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
include/drm/intel/mchbar_regs.h
258
#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
include/drm/intel/mchbar_regs.h
259
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
include/drm/intel/mchbar_regs.h
266
#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5f0c)
include/drm/intel/mchbar_regs.h
271
#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)