drivers/gpu/drm/i915/display/intel_mchbar.c

24

return MCHBAR_MIRROR_BASE;

include/drm/intel/mchbar_regs.h

30

#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)

include/drm/intel/mchbar_regs.h

31

#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)

include/drm/intel/mchbar_regs.h

37

#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)

include/drm/intel/mchbar_regs.h

41

#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)

include/drm/intel/mchbar_regs.h

48

#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)

include/drm/intel/mchbar_regs.h

52

#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)

include/drm/intel/mchbar_regs.h

53

#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)

include/drm/intel/mchbar_regs.h

56

#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)

include/drm/intel/mchbar_regs.h

73

#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)

include/drm/intel/mchbar_regs.h

74

#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)

include/drm/intel/mchbar_regs.h

76

#define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)

include/drm/intel/mchbar_regs.h

78

#define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)

include/drm/intel/mchbar_regs.h

79

#define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)

include/drm/intel/mchbar_regs.h

85

#define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222)

include/drm/intel/mchbar_regs.h

90

#define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)

include/drm/intel/mchbar_regs.h

91

#define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)

include/drm/intel/mchbar_regs.h

93

#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)