MCR
writel(0x00, UART1_REG(MCR));
writel(0x00, UART1_REG(MCR));
writel(0x00, UART1_REG(MCR));
mcr = __raw_readw(MCR);
__raw_writew(mcr & ~MCR_RFSH, MCR);
__raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
outb(0x3, port + MCR); /* DTR + RTS */
static_call(serial_out)(early_serial_base, MCR, 0x3); /* DTR + RTS */
PUT( walk->old_mcr ,MCR);
PRIV(dev)->old_mcr = GET(MCR);
) & ~IDT77105_MCR_EIP, MCR);
PRIV(dev)->old_mcr = GET(MCR);
PUT(PRIV(dev)->old_mcr, MCR);
PUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR );
uart_config.mcr.value = __cpu_to_le32(MCR);
dma_writel(ddev, MCR, 0);
dma_writel(ddev, MCR, mcr);
dma_writel(ddev, MCR, mcr);
mcr = dma_readl(ddev, MCR);
dma_readl(ddev, MCR));
u32 MCR;
TXX9_DMA_REG32(MCR); /* Master Control Register */
memory_cfg_register = inw( ioaddr + MCR );
outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr));
outb(0x0d, MCR(dev->base_addr)); /* transmitter off */
b1 = inb(MCR(iobase));
outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
outb(0x1a, MCR(iobase));
outb(b1, MCR(iobase)); /* restore old values */
outb(0x0d, MCR(dev->base_addr));
outb(1, MCR(dev->base_addr));
outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr));
outb(0x0d, MCR(dev->base_addr)); /* transmitter off */
b1 = inb(MCR(iobase));
outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
outb(0x1a, MCR(iobase));
outb(b1, MCR(iobase)); /* restore old values */
outb(0x0d, MCR(dev->base_addr));
outb(1, MCR(dev->base_addr));
outb(MCR_OUT1 | MCR_OUT2, MCR(iobase));
outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase));
outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase));
outb(PTT_OFF, MCR(dev->base_addr));
b1 = inb(MCR(iobase));
outb(b1 | 0x10, MCR(iobase)); /* loopback mode */
outb(0x1a, MCR(iobase));
outb(b1, MCR(iobase)); /* restore old values */
outb(PTT_ON, MCR(dev->base_addr));
outb(PTT_OFF, MCR(dev->base_addr));
outb(1, MCR(dev->base_addr));
writel(0x00, UART1_REG(MCR));
control = info->MCR;
info->MCR |= SER_RTS;
info->MCR |= SER_DTR;
info->MCR &= ~SER_RTS;
info->MCR &= ~SER_DTR;
rtsdtr_ctrl(info->MCR);
info->MCR &= ~(SER_DTR|SER_RTS);
rtsdtr_ctrl(info->MCR);
info->MCR |= SER_DTR;
info->MCR |= SER_RTS;
rtsdtr_ctrl(info->MCR);
control = tty_port_initialized(&state->tport) ? state->MCR : status;
info->MCR |= SER_DTR|SER_RTS;
info->MCR &= ~(SER_DTR|SER_RTS);
rtsdtr_ctrl(info->MCR);
info->MCR = 0;
info->MCR = SER_DTR | SER_RTS;
rtsdtr_ctrl(info->MCR);
info->MCR &= ~(SER_DTR|SER_RTS);
rtsdtr_ctrl(info->MCR);
int MCR; /* Modem control register */
info->MCR &= ~SER_RTS;
rtsdtr_ctrl(info->MCR);
info->MCR |= SER_RTS;
rtsdtr_ctrl(info->MCR);
control = info->MCR;
info->MCR |= UART_MCR_RTS;
info->MCR |= UART_MCR_DTR;
info->MCR &= ~UART_MCR_RTS;
info->MCR &= ~UART_MCR_DTR;
outb(info->MCR, info->ioaddr + UART_MCR);
info->MCR &= ~UART_MCR_RTS;
outb(info->MCR, info->ioaddr + UART_MCR);
info->MCR |= UART_MCR_RTS;
outb(info->MCR, info->ioaddr + UART_MCR);
u8 MCR; /* Modem control register */
info->MCR |= UART_MCR_DTR;
outb(info->MCR, info->ioaddr + UART_MCR);
info->MCR &= ~UART_MCR_DTR;
outb(info->MCR, info->ioaddr + UART_MCR);
info->MCR &= ~UART_MCR_AFE;
info->MCR |= UART_MCR_AFE;
outb(info->MCR, info->ioaddr + UART_MCR);
info->MCR = UART_MCR_DTR | UART_MCR_RTS;
outb(info->MCR, info->ioaddr + UART_MCR);
status = send_cmd_write_uart_register(edge_port, MCR,
send_cmd_write_uart_register(edge_port, MCR,
send_cmd_write_uart_register(edge_port, MCR, edge_port->shadowMCR);
(regNum == MCR) ? "MCR" : "LCR", __func__, regValue);
regNum == MCR) {
status = send_cmd_write_uart_register(edge_port, MCR,