MCLK
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, CLOCK_FCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
CLK_MAP(MCLK, PPCLK_UCLK),
static const u32 MCLK = (1550000000 / 12);
if (p->symbol_rate >= (MCLK / 2))
if (p->symbol_rate >= MCLK / 2) {
i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7;
mclken_div = 512000000 / MCLK;
ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
ccr |= (MCLK / 1000000 - 1) & 0xFF;
u16 MCLK;
#define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
int MCLK, REFCLK, LCDclk;
if (par->MCLK <= 0) {
common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
par->MCLK);
SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK,
idx1 = longtemp % (MCLK * 16);
longtemp /= (MCLK * 16);
unsigned short colordepth, unsigned short MCLK)
temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0);
temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1);
unsigned short temp, index, VCLK, MCLK, colorth;
MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1;
unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0;
MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
data2 = temp - ((colorth * VCLK) / MCLK);
temp = data % (MCLK << 4);
data = data / (MCLK << 4);
fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate);
ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq);
ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate);
ret = clk_set_parent(aiu->spdif.clks[MCLK].clk,
[MCLK] = "i2s_mclk",
[MCLK] = "spdif_mclk_sel"