arch/x86/kernel/cpu/mce/intel.c

145

val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;

arch/x86/kernel/cpu/mce/intel.c

208

if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD)

arch/x86/kernel/cpu/mce/intel.c

212

val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;

arch/x86/kernel/cpu/mce/intel.c

214

} else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {

arch/x86/kernel/cpu/mce/intel.c

248

if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) {

arch/x86/kernel/cpu/mce/intel.c

263

(val & MCI_CTL2_CMCI_THRESHOLD_MASK))

arch/x86/kernel/cpu/mce/intel.c

268

cmci_threshold[bank] = val & MCI_CTL2_CMCI_THRESHOLD_MASK;

arch/x86/kernel/cpu/mce/intel.c

332

if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD)

arch/x86/kvm/x86.c

3585

if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))